1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.util._ 6import org.chipsalliance.cde.config.Parameters 7import xiangshan.backend.fu.NewCSR.CSRDefines.{ 8 CSRRWField => RW, 9 CSRROField => RO, 10} 11import xiangshan.HasXSParameter 12 13import scala.collection.immutable.SeqMap 14 15trait CSRCustom { self: NewCSR => 16 // Supervisor Custom Read/Write 17 val sbpctl = Module(new CSRModule("Sbpctl", new SbpctlBundle)) 18 .setAddr(0x5C0) 19 20 val spfctl = Module(new CSRModule("Spfctl", new SpfctlBundle)) 21 .setAddr(0x5C1) 22 23 // slvpredctl: load violation predict settings 24 // Default reset period: 2^16 25 // why this number: reset more frequently while keeping the overhead low 26 // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead 27 val slvpredctl = Module(new CSRModule("Slvpredctl", new SlvpredctlBundle)) 28 .setAddr(0x5C2) 29 30 // smblockctl: memory block configurations 31 val smblockctl = Module(new CSRModule("Smblockctl", new SmblockctlBundle)) 32 .setAddr(0x5C3) 33 34 val srnctl = Module(new CSRModule("Srnctl", new SrnctlBundle)) 35 .setAddr(0x5C4) 36 37 // Machine Level Custom Read/Write 38 39 // mcorepwr: Core Power Down Status Enable 40 val mcorepwr = Module(new CSRModule("Mcorepwr", new McorepwrBundle)) 41 .setAddr(0xBC0) 42 43 // mflushpwr: Flush L2 Cache Enable 44 val mflushpwr = Module(new CSRModule("Mflushpwr", new MflushpwrBundle) 45 with HasMachineFlushL2Bundle 46 { 47 regOut.L2_FLUSH_DONE := l2FlushDone 48 }) 49 .setAddr(0xBC1) 50 51 val customCSRMods = Seq( 52 sbpctl, 53 spfctl, 54 slvpredctl, 55 smblockctl, 56 srnctl, 57 mcorepwr, 58 mflushpwr, 59 ) 60 61 val customCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], UInt)] = SeqMap.from( 62 customCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata))).iterator 63 ) 64 65 val customCSROutMap: SeqMap[Int, UInt] = SeqMap.from( 66 customCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator 67 ) 68} 69 70class SbpctlBundle extends CSRBundle { 71 val LOOP_ENABLE = RW(6).withReset(true.B) 72 val RAS_ENABLE = RW(5).withReset(true.B) 73 val SC_ENABLE = RW(4).withReset(true.B) 74 val TAGE_ENABLE = RW(3).withReset(true.B) 75 val BIM_ENABLE = RW(2).withReset(true.B) 76 val BTB_ENABLE = RW(1).withReset(true.B) 77 val UBTB_ENABLE = RW(0).withReset(true.B) 78} 79 80class SpfctlBundle extends CSRBundle { 81 val L2_PF_TP_ENABLE = RW( 21).withReset(true.B) // (Train L2, Prefetch L2) TP 82 val L2_PF_VBOP_ENABLE = RW( 20).withReset(true.B) // (Train L2, Prefetch L2) VBOP 83 val L2_PF_PBOP_ENABLE = RW( 19).withReset(true.B) // (Train L2, Prefetch L2) PBOP 84 val L2_PF_RECV_ENABLE = RW( 18).withReset(true.B) // (Train L1, Prefetch L2) receive from sms 85 val L2_PF_STORE_ONLY = RW( 17).withReset(false.B) // L2 pf store only 86 val L1D_PF_ENABLE_STRIDE = RW( 16).withReset(true.B) // L1D prefetch enable stride 87 val L1D_PF_ACTIVE_STRIDE = SpfctlL1DPfActiveStride(15, 10).withReset(SpfctlL1DPfActiveStride.initValue) // L1D prefetch active page stride 88 val L1D_PF_ACTIVE_THRESHOLD = SpfctlL1DPfActiveThreshold( 9, 6).withReset(SpfctlL1DPfActiveThreshold.initValue) // L1D prefetch active page threshold 89 val L1D_PF_ENABLE_PHT = RW( 5).withReset(true.B) // L1D prefetch enable pht 90 val L1D_PF_ENABLE_AGT = RW( 4).withReset(true.B) // L1D prefetch enable agt 91 val L1D_PF_TRAIN_ON_HIT = RW( 3).withReset(false.B) // L1D train prefetch on hit 92 val L1D_PF_ENABLE = RW( 2).withReset(true.B) // L1D Cache Prefetcher Enable 93 val L2_PF_ENABLE = RW( 1).withReset(true.B) // L2 Cache Prefetcher master Enable 94 val L1I_PF_ENABLE = RW( 0).withReset(true.B) // L1I Cache Prefetcher Enable 95} 96 97class SlvpredctlBundle extends CSRBundle { 98 val LVPRED_TIMEOUT = SlvpredCtlTimeOut(8, 4).withReset(SlvpredCtlTimeOut.initValue) 99 val STORESET_NO_FAST_WAKEUP = RW(3).withReset(false.B) 100 val STORESET_WAIT_STORE = RW(2).withReset(false.B) 101 val NO_SPEC_LOAD = RW(1).withReset(false.B) 102 val LVPRED_DISABLE = RW(0).withReset(false.B) 103} 104 105class SmblockctlBundle extends CSRBundle { 106 val HD_MISALIGN_LD_ENABLE = RW( 9).withReset(true.B) // Enable hardware load misalign. 107 val HD_MISALIGN_ST_ENABLE = RW( 8).withReset(true.B) // Enable hardware store misalign. 108 val UNCACHE_WRITE_OUTSTANDING_ENABLE = RW( 7).withReset(false.B) // Enable uncache write outstanding (0). 109 val CACHE_ERROR_ENABLE = RW( 6).withReset(true.B) // Enable cache error after reset (CE). 110 val SOFT_PREFETCH_ENABLE = RW( 5).withReset(true.B) // Enable soft-prefetch after reset (SP). 111 val LDLD_VIO_CHECK_ENABLE = RW( 4).withReset(true.B) // Enable load load violation check after reset (LVC). 112 val SBUFFER_THRESHOLD = SbufferThreshold(3, 0).withReset(SbufferThreshold.initValue) // Store buffer flush threshold (Th). 113} 114 115class SrnctlBundle extends CSRBundle { 116 val WFI_ENABLE = RW(2).withReset(true.B) 117 val FUSION_ENABLE = RW(0).withReset(true.B) 118} 119 120class McorepwrBundle extends CSRBundle { 121 val POWER_DOWN_ENABLE = RW(0).withReset(false.B) 122} 123 124class MflushpwrBundle extends CSRBundle { 125 val FLUSH_L2_ENABLE = RW(0).withReset(false.B) 126 val L2_FLUSH_DONE = RO(1).withReset(false.B) 127} 128 129object SbufferThreshold extends CSREnum with RWApply { 130 val initValue = Value(7.U) 131} 132 133object SpfctlL1DPfActiveStride extends CSREnum with RWApply { 134 val initValue = Value(30.U) 135} 136 137object SpfctlL1DPfActiveThreshold extends CSREnum with RWApply { 138 val initValue = Value(12.U) 139} 140 141object SlvpredCtlTimeOut extends CSREnum with RWApply { 142 val initValue = Value(3.U) 143} 144 145