1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28} 29 30case class CertainLatency(value: Int) extends HasFuLatency { 31 override val latencyVal: Option[Int] = Some(value) 32} 33 34case class UncertainLatency() extends HasFuLatency { 35 override val latencyVal: Option[Int] = None 36} 37 38 39case class FuConfig 40( 41 name: String, 42 fuGen: Parameters => FunctionUnit, 43 fuSel: MicroOp => Bool, 44 fuType: UInt, 45 numIntSrc: Int, 46 numFpSrc: Int, 47 numVecSrc: Int = 0, 48 writeIntRf: Boolean, 49 writeFpRf: Boolean, 50 writeVecRf: Boolean = false, 51 writeFflags: Boolean = false, 52 writeVxsat: Boolean = false, 53 hasRedirect: Boolean = false, 54 latency: HasFuLatency = CertainLatency(0), 55 fastUopOut: Boolean = false, 56 fastImplemented: Boolean = false, 57 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 58 exceptionOut: Seq[Int] = Seq(), 59 hasLoadError: Boolean = false, 60 flushPipe: Boolean = false, 61 replayInst: Boolean = false, 62 trigger: Boolean = false 63) { 64 def srcCnt: Int = math.max(math.max(numIntSrc, numFpSrc), numVecSrc) 65 def isVectorFU: Boolean = (numVecSrc > 0) && writeVecRf 66 67 // require(numFpSrc == 0 || numVecSrc == 0, "numVecSrc+numFpSrc is not handled now. It's forbidden until someone add support for numVecSrc+numFpSrc") 68 69 override def toString: String = { 70 s"${name}: SrcNum(${numIntSrc}|${numFpSrc}|${numVecSrc}) " + 71 s"Write(" + 72 (if(writeIntRf) "int|" else "") + 73 (if(writeFpRf) "fp|" else "") + 74 (if(writeVecRf) "vec|" else "") + 75 (if(writeFflags) "fflags" else "") + 76 (if(writeVxsat) "vxsat" else "") + 77 (if(!writeIntRf && !writeFpRf && !writeVecRf && !writeFflags && !writeVxsat) "none" else "") + ") " + 78 (if(hasRedirect) "hasRedirect " else "") + 79 (if(latency.latencyVal.getOrElse(99) != 99) "latency " + latency.latencyVal.get+" " else "") + 80 (if(fastUopOut) "hasFastUopOut " else "") + 81 s"inputBuffer (${hasInputBuffer._1},${hasInputBuffer._2},${hasInputBuffer._3}) " 82 } 83} 84 85 86class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 87 val data = UInt(len.W) 88 val uop = new MicroOp 89} 90 91class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 92 val src = Vec(4, UInt(len.W)) 93 val uop = new MicroOp 94} 95 96class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 97 val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 98 99 val out = DecoupledIO(new FuOutput(len)) 100 101 val redirectIn = Flipped(ValidIO(new Redirect)) 102} 103 104abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 105 106 val io = IO(new FunctionUnitIO(len)) 107 108 XSPerfAccumulate("in_valid", io.in.valid) 109 XSPerfAccumulate("in_fire", io.in.fire) 110 XSPerfAccumulate("out_valid", io.out.valid) 111 XSPerfAccumulate("out_fire", io.out.fire) 112 113} 114 115abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut 116 117trait HasPipelineReg { 118 this: FunctionUnit => 119 120 def latency: Int 121 122 require(latency > 0) 123 124 val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 125 val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B) 126 val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp)) 127 128 129 // if flush(0), valid 0 will not given, so set flushVec(0) to false.B 130 val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.robIdx.needFlush(io.redirectIn)) 131 132 for (i <- 0 until latency - 1) { 133 rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1) 134 } 135 136 for (i <- 1 to latency) { 137 when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){ 138 validVec(i) := validVec(i - 1) 139 uopVec(i) := uopVec(i - 1) 140 }.elsewhen(flushVec(i) || rdyVec(i)){ 141 validVec(i) := false.B 142 } 143 } 144 145 io.in.ready := rdyVec(0) 146 io.out.valid := validVec.takeRight(2).head 147 io.out.bits.uop := uopVec.takeRight(2).head 148 149 def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1) 150 151 def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable( 152 next, 153 regEnable(i) 154 ) 155 156 def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next) 157 158 def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next) 159 160 def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next) 161 162 def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next) 163 164 def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next) 165} 166