xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala (revision a63155a6a44b3c7714e55906b55ebf92e0efc125) 
1package xiangshan.backend.fu
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.DataHoldBypass
7import utils.OptionWrapper
8import xiangshan._
9import xiangshan.backend.Bundles.VPUCtrlSignals
10import xiangshan.backend.rob.RobPtr
11import xiangshan.frontend.{FtqPtr, PreDecodeInfo}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.fu.vector.Bundles.Vxsat
14import xiangshan.ExceptionNO.illegalInstr
15
16class FuncUnitCtrlInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
17  val fuOpType    = FuOpType()
18  val robIdx      = new RobPtr
19  val pdest       = UInt(PhyRegIdxWidth.W)
20  val rfWen       = OptionWrapper(cfg.writeIntRf, Bool())
21  val fpWen       = OptionWrapper(cfg.writeFpRf,  Bool())
22  val vecWen      = OptionWrapper(cfg.writeVecRf, Bool())
23  val flushPipe   = OptionWrapper(cfg.flushPipe,  Bool())
24  val preDecode   = OptionWrapper(cfg.hasPredecode, new PreDecodeInfo)
25  val ftqIdx      = OptionWrapper(cfg.needPc || cfg.replayInst, new FtqPtr)
26  val ftqOffset   = OptionWrapper(cfg.needPc || cfg.replayInst, UInt(log2Up(PredictWidth).W))
27  val predictInfo = OptionWrapper(cfg.hasRedirect, new Bundle {
28    val target    = UInt(VAddrData().dataWidth.W)
29    val taken     = Bool()
30  })
31  val fpu         = OptionWrapper(cfg.writeFflags, new FPUCtrlSignals)
32  val vpu         = OptionWrapper(cfg.needVecCtrl, new VPUCtrlSignals)
33}
34
35class FuncUnitCtrlOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
36  val robIdx        = new RobPtr
37  val pdest         = UInt(PhyRegIdxWidth.W) // Todo: use maximum of pregIdxWidth of different pregs
38  val rfWen         = OptionWrapper(cfg.writeIntRf, Bool())
39  val fpWen         = OptionWrapper(cfg.writeFpRf,  Bool())
40  val vecWen        = OptionWrapper(cfg.writeVecRf, Bool())
41  val exceptionVec  = OptionWrapper(cfg.exceptionOut.nonEmpty, ExceptionVec())
42  val flushPipe     = OptionWrapper(cfg.flushPipe,  Bool())
43  val replay        = OptionWrapper(cfg.replayInst, Bool())
44  val preDecode     = OptionWrapper(cfg.hasPredecode, new PreDecodeInfo)
45  val fpu           = OptionWrapper(cfg.writeFflags, new FPUCtrlSignals)
46  val vpu           = OptionWrapper(cfg.needVecCtrl, new VPUCtrlSignals)
47}
48
49class FuncUnitDataInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
50  val src       = MixedVec(cfg.genSrcDataVec)
51  val imm       = UInt(cfg.dataBits.W)
52  val pc        = OptionWrapper(cfg.needPc, UInt(VAddrData().dataWidth.W))
53
54  def getSrcVConfig : UInt = src(cfg.vconfigIdx)
55  def getSrcMask    : UInt = src(cfg.maskSrcIdx)
56}
57
58class FuncUnitDataOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
59  val data      = UInt(cfg.dataBits.W)
60  val fflags    = OptionWrapper(cfg.writeFflags, UInt(5.W))
61  val vxsat     = OptionWrapper(cfg.writeVxsat, Vxsat())
62  val pc        = OptionWrapper(cfg.isFence, UInt(VAddrData().dataWidth.W))
63  val redirect  = OptionWrapper(cfg.hasRedirect, ValidIO(new Redirect))
64}
65
66class FuncUnitInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
67  val ctrl = new FuncUnitCtrlInput(cfg)
68  val data = new FuncUnitDataInput(cfg)
69}
70
71class FuncUnitOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
72  val ctrl = new FuncUnitCtrlOutput(cfg)
73  val res = new FuncUnitDataOutput(cfg)
74}
75
76class FuncUnitIO(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
77  val flush = Flipped(ValidIO(new Redirect))
78  val in = Flipped(DecoupledIO(new FuncUnitInput(cfg)))
79  val out = DecoupledIO(new FuncUnitOutput(cfg))
80  val csrio = if (cfg.isCsr) Some(new CSRFileIO) else None
81  val fenceio = if (cfg.isFence) Some(new FenceIO) else None
82  val frm = if (cfg.needSrcFrm) Some(Input(UInt(3.W))) else None
83}
84
85abstract class FuncUnit(val cfg: FuConfig)(implicit p: Parameters) extends XSModule {
86  val io = IO(new FuncUnitIO(cfg))
87
88  // should only be used in non-piped fu
89  def connectNonPipedCtrlSingal: Unit = {
90    io.out.bits.ctrl.robIdx := DataHoldBypass(io.in.bits.ctrl.robIdx, io.in.fire)
91    io.out.bits.ctrl.pdest  := DataHoldBypass(io.in.bits.ctrl.pdest, io.in.fire)
92    io.out.bits.ctrl.rfWen  .foreach(_ := DataHoldBypass(io.in.bits.ctrl.rfWen.get, io.in.fire))
93    io.out.bits.ctrl.fpWen  .foreach(_ := DataHoldBypass(io.in.bits.ctrl.fpWen.get, io.in.fire))
94    io.out.bits.ctrl.vecWen .foreach(_ := DataHoldBypass(io.in.bits.ctrl.vecWen.get, io.in.fire))
95    // io.out.bits.ctrl.flushPipe should be connected in fu
96    io.out.bits.ctrl.preDecode.foreach(_ := DataHoldBypass(io.in.bits.ctrl.preDecode.get, io.in.fire))
97    io.out.bits.ctrl.fpu      .foreach(_ := DataHoldBypass(io.in.bits.ctrl.fpu.get, io.in.fire))
98    io.out.bits.ctrl.vpu      .foreach(_ := DataHoldBypass(io.in.bits.ctrl.vpu.get, io.in.fire))
99  }
100}
101
102/**
103  * @author LinJiaWei, Yinan Xu
104  */
105trait HasPipelineReg { this: FuncUnit =>
106  def latency: Int
107
108  require(latency >= 0)
109
110  val validVec = io.in.valid +: Seq.fill(latency)(RegInit(false.B))
111  val rdyVec = Seq.fill(latency)(Wire(Bool())) :+ io.out.ready
112  val ctrlVec = io.in.bits.ctrl +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.ctrl)))
113  val dataVec = io.in.bits.data +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.data)))
114
115  val robIdxVec = ctrlVec.map(_.robIdx)
116  val pcVec = dataVec.map(_.pc)
117
118  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
119  val flushVec = validVec.zip(robIdxVec).map(x => x._1 && x._2.needFlush(io.flush))
120
121  for (i <- 0 until latency) {
122    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
123  }
124
125  for (i <- 1 to latency) {
126    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)) {
127      validVec(i) := validVec(i - 1)
128      ctrlVec(i) := ctrlVec(i - 1)
129      dataVec(i) := dataVec(i - 1)
130    }.elsewhen(flushVec(i) || rdyVec(i)) {
131      validVec(i) := false.B
132    }
133  }
134
135  io.in.ready := rdyVec.head
136  io.out.valid := validVec.last
137  io.out.bits.res.pc.zip(pcVec.last).foreach { case (l, r) => l := r }
138
139  io.out.bits.ctrl.robIdx := ctrlVec.last.robIdx
140  io.out.bits.ctrl.pdest := ctrlVec.last.pdest
141  io.out.bits.ctrl.rfWen.foreach(_ := ctrlVec.last.rfWen.get)
142  io.out.bits.ctrl.fpWen.foreach(_ := ctrlVec.last.fpWen.get)
143  io.out.bits.ctrl.vecWen.foreach(_ := ctrlVec.last.vecWen.get)
144  io.out.bits.ctrl.fpu.foreach(_ := ctrlVec.last.fpu.get)
145  io.out.bits.ctrl.vpu.foreach(_ := ctrlVec.last.vpu.get)
146
147  // vstart illegal
148  if (cfg.exceptionOut.nonEmpty) {
149    val outVstart = ctrlVec.last.vpu.get.vstart
150    val vstartIllegal = outVstart =/= 0.U
151    io.out.bits.ctrl.exceptionVec.get := 0.U.asTypeOf(io.out.bits.ctrl.exceptionVec.get)
152    io.out.bits.ctrl.exceptionVec.get(illegalInstr) := vstartIllegal
153  }
154
155  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
156
157  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
158    next,
159    regEnable(i)
160  )
161
162  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
163
164  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
165
166  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
167
168  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
169
170  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
171
172}
173
174abstract class PipedFuncUnit(override val cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
175  with HasPipelineReg {
176  override def latency: Int = cfg.latency.latencyVal.get
177}
178