xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala (revision 9e200047e3e84d1588ae9ea8bd96d3eade2c7638) 
1package xiangshan.backend.fu
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.DataHoldBypass
7import utils.OptionWrapper
8import xiangshan._
9import xiangshan.backend.Bundles.VPUCtrlSignals
10import xiangshan.backend.rob.RobPtr
11import xiangshan.frontend.{FtqPtr, PreDecodeInfo}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.fu.vector.Bundles.Vxsat
14import xiangshan.ExceptionNO.illegalInstr
15import xiangshan.backend.fu.vector.Bundles.VType
16
17class FuncUnitCtrlInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
18  val fuOpType    = FuOpType()
19  val robIdx      = new RobPtr
20  val pdest       = UInt(PhyRegIdxWidth.W)
21  val rfWen       = OptionWrapper(cfg.needIntWen, Bool())
22  val fpWen       = OptionWrapper(cfg.needFpWen,  Bool())
23  val vecWen      = OptionWrapper(cfg.needVecWen, Bool())
24  val flushPipe   = OptionWrapper(cfg.flushPipe,  Bool())
25  val preDecode   = OptionWrapper(cfg.hasPredecode, new PreDecodeInfo)
26  val ftqIdx      = OptionWrapper(cfg.needPc || cfg.replayInst || cfg.isSta, new FtqPtr)
27  val ftqOffset   = OptionWrapper(cfg.needPc || cfg.replayInst || cfg.isSta, UInt(log2Up(PredictWidth).W))
28  val predictInfo = OptionWrapper(cfg.hasRedirect, new Bundle {
29    val target    = UInt(VAddrData().dataWidth.W)
30    val taken     = Bool()
31  })
32  val fpu         = OptionWrapper(cfg.writeFflags, new FPUCtrlSignals)
33  val vpu         = OptionWrapper(cfg.needVecCtrl, new VPUCtrlSignals)
34}
35
36class FuncUnitCtrlOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
37  val robIdx        = new RobPtr
38  val pdest         = UInt(PhyRegIdxWidth.W) // Todo: use maximum of pregIdxWidth of different pregs
39  val rfWen         = OptionWrapper(cfg.needIntWen, Bool())
40  val fpWen         = OptionWrapper(cfg.needFpWen,  Bool())
41  val vecWen        = OptionWrapper(cfg.needVecWen, Bool())
42  val exceptionVec  = OptionWrapper(cfg.exceptionOut.nonEmpty, ExceptionVec())
43  val flushPipe     = OptionWrapper(cfg.flushPipe,  Bool())
44  val replay        = OptionWrapper(cfg.replayInst, Bool())
45  val preDecode     = OptionWrapper(cfg.hasPredecode, new PreDecodeInfo)
46  val fpu           = OptionWrapper(cfg.writeFflags, new FPUCtrlSignals)
47  val vpu           = OptionWrapper(cfg.needVecCtrl, new VPUCtrlSignals)
48}
49
50class FuncUnitDataInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
51  val src       = MixedVec(cfg.genSrcDataVec)
52  val imm       = UInt(cfg.dataBits.W)
53  val pc        = OptionWrapper(cfg.needPc, UInt(VAddrData().dataWidth.W))
54
55  def getSrcVConfig : UInt = src(cfg.vconfigIdx)
56  def getSrcMask    : UInt = src(cfg.maskSrcIdx)
57}
58
59class FuncUnitDataOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
60  val data      = UInt(cfg.dataBits.W)
61  val fflags    = OptionWrapper(cfg.writeFflags, UInt(5.W))
62  val vxsat     = OptionWrapper(cfg.writeVxsat, Vxsat())
63  val pc        = OptionWrapper(cfg.isFence, UInt(VAddrData().dataWidth.W))
64  val redirect  = OptionWrapper(cfg.hasRedirect, ValidIO(new Redirect))
65}
66
67class FuncUnitInput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
68  val ctrl = new FuncUnitCtrlInput(cfg)
69  val data = new FuncUnitDataInput(cfg)
70  val perfDebugInfo = new PerfDebugInfo()
71}
72
73class FuncUnitOutput(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
74  val ctrl = new FuncUnitCtrlOutput(cfg)
75  val res = new FuncUnitDataOutput(cfg)
76  val perfDebugInfo = new PerfDebugInfo()
77}
78
79class FuncUnitIO(cfg: FuConfig)(implicit p: Parameters) extends XSBundle {
80  val flush = Flipped(ValidIO(new Redirect))
81  val in = Flipped(DecoupledIO(new FuncUnitInput(cfg)))
82  val out = DecoupledIO(new FuncUnitOutput(cfg))
83  val csrio = OptionWrapper(cfg.isCsr, new CSRFileIO)
84  val fenceio = OptionWrapper(cfg.isFence, new FenceIO)
85  val frm = OptionWrapper(cfg.needSrcFrm, Input(UInt(3.W)))
86  val vxrm = OptionWrapper(cfg.needSrcVxrm, Input(UInt(2.W)))
87  val vtype = OptionWrapper(cfg.writeVType, new VType)
88}
89
90abstract class FuncUnit(val cfg: FuConfig)(implicit p: Parameters) extends XSModule {
91  val io = IO(new FuncUnitIO(cfg))
92
93  // should only be used in non-piped fu
94  def connectNonPipedCtrlSingal: Unit = {
95    io.out.bits.ctrl.robIdx := RegEnable(io.in.bits.ctrl.robIdx, io.in.fire)
96    io.out.bits.ctrl.pdest  := RegEnable(io.in.bits.ctrl.pdest, io.in.fire)
97    io.out.bits.ctrl.rfWen  .foreach(_ := RegEnable(io.in.bits.ctrl.rfWen.get, io.in.fire))
98    io.out.bits.ctrl.fpWen  .foreach(_ := RegEnable(io.in.bits.ctrl.fpWen.get, io.in.fire))
99    io.out.bits.ctrl.vecWen .foreach(_ := RegEnable(io.in.bits.ctrl.vecWen.get, io.in.fire))
100    // io.out.bits.ctrl.flushPipe should be connected in fu
101    io.out.bits.ctrl.preDecode.foreach(_ := RegEnable(io.in.bits.ctrl.preDecode.get, io.in.fire))
102    io.out.bits.ctrl.fpu      .foreach(_ := RegEnable(io.in.bits.ctrl.fpu.get, io.in.fire))
103    io.out.bits.ctrl.vpu      .foreach(_ := RegEnable(io.in.bits.ctrl.vpu.get, io.in.fire))
104    io.out.bits.perfDebugInfo := RegEnable(io.in.bits.perfDebugInfo, io.in.fire)
105  }
106
107  def connect0LatencyCtrlSingal: Unit = {
108    io.out.bits.ctrl.robIdx := io.in.bits.ctrl.robIdx
109    io.out.bits.ctrl.pdest := io.in.bits.ctrl.pdest
110    io.out.bits.ctrl.rfWen.foreach(_ := io.in.bits.ctrl.rfWen.get)
111    io.out.bits.ctrl.fpWen.foreach(_ := io.in.bits.ctrl.fpWen.get)
112    io.out.bits.ctrl.vecWen.foreach(_ := io.in.bits.ctrl.vecWen.get)
113    // io.out.bits.ctrl.flushPipe should be connected in fu
114    io.out.bits.ctrl.preDecode.foreach(_ := io.in.bits.ctrl.preDecode.get)
115    io.out.bits.ctrl.fpu.foreach(_ := io.in.bits.ctrl.fpu.get)
116    io.out.bits.ctrl.vpu.foreach(_ := io.in.bits.ctrl.vpu.get)
117    io.out.bits.perfDebugInfo := io.in.bits.perfDebugInfo
118  }
119}
120
121/**
122  * @author LinJiaWei, Yinan Xu
123  */
124trait HasPipelineReg { this: FuncUnit =>
125  def latency: Int
126
127  val latdiff :Int = cfg.latency.extraLatencyVal.getOrElse(0)
128  val preLat :Int = latency - latdiff
129  require(latency >= 0 && latdiff >=0)
130
131  def pipelineReg(init: FuncUnitInput , valid:Bool, ready: Bool,latency: Int, flush:ValidIO[Redirect]): (Seq[FuncUnitInput],Seq[Bool],Seq[Bool])={
132    val rdyVec = Seq.fill(latency)(Wire(Bool())) :+ ready
133    val validVec = valid +: Seq.fill(latency)(RegInit(false.B))
134    val ctrlVec = init.ctrl +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.ctrl)))
135    val dataVec = init.data +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.data)))
136    val perfVec = init.perfDebugInfo +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.perfDebugInfo)))
137
138
139
140    val robIdxVec = ctrlVec.map(_.robIdx)
141
142    // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
143    val flushVec = validVec.zip(robIdxVec).map(x => x._1 && x._2.needFlush(flush))
144
145    for (i <- 0 until latency) {
146      rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1).asTypeOf(Bool())
147    }
148    for (i <- 1 to latency) {
149      when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)) {
150        validVec(i) := validVec(i - 1)
151        ctrlVec(i) := ctrlVec(i - 1)
152        dataVec(i) := dataVec(i - 1)
153        perfVec(i) := perfVec(i - 1)
154      }.elsewhen(flushVec(i) || rdyVec(i)) {
155        validVec(i) := false.B
156      }
157    }
158
159    (ctrlVec.zip(dataVec).zip(perfVec).map{
160      case(( ctrl,data), perf) => {
161        val out = Wire(new FuncUnitInput(cfg))
162        out.ctrl := ctrl
163        out.data := data
164        out.perfDebugInfo := perf
165        out
166      }
167    },validVec, rdyVec)
168  }
169  val (pipeReg : Seq[FuncUnitInput],validVec ,rdyVec ) = pipelineReg(io.in.bits, io.in.valid,io.out.ready,preLat, io.flush)
170  val ctrlVec = pipeReg.map(_.ctrl)
171  val dataVec = pipeReg.map(_.data)
172  val perfVec = pipeReg.map(_.perfDebugInfo)
173  val robIdxVec = ctrlVec.map(_.robIdx)
174  val pipeflushVec = validVec.zip(robIdxVec).map(x => x._1 && x._2.needFlush(io.flush))
175
176
177  val fixtiminginit = Wire(new FuncUnitInput(cfg))
178  fixtiminginit.ctrl := ctrlVec.last
179  fixtiminginit.data := dataVec.last
180  fixtiminginit.perfDebugInfo := perfVec.last
181
182  // fixtiming pipelinereg
183  val (fixpipeReg : Seq[FuncUnitInput], fixValidVec, fixRdyVec) = pipelineReg(fixtiminginit, validVec.last,rdyVec.head ,latdiff, io.flush)
184  val fixCtrlVec = fixpipeReg.map(_.ctrl)
185  val fixDataVec = fixpipeReg.map(_.data)
186  val fixPerfVec = fixpipeReg.map(_.perfDebugInfo)
187  val fixrobIdxVec = ctrlVec.map(_.robIdx)
188  val fixflushVec = fixValidVec.zip(fixrobIdxVec).map(x => x._1 && x._2.needFlush(io.flush))
189  val flushVec = pipeflushVec ++ fixflushVec
190  val pcVec = fixDataVec.map(_.pc)
191
192  io.in.ready := fixRdyVec.head
193  io.out.valid := fixValidVec.last
194  io.out.bits.res.pc.zip(pcVec.last).foreach { case (l, r) => l := r }
195
196  io.out.bits.ctrl.robIdx := fixCtrlVec.last.robIdx
197  io.out.bits.ctrl.pdest := fixCtrlVec.last.pdest
198  io.out.bits.ctrl.rfWen.foreach(_ := fixCtrlVec.last.rfWen.get)
199  io.out.bits.ctrl.fpWen.foreach(_ := fixCtrlVec.last.fpWen.get)
200  io.out.bits.ctrl.vecWen.foreach(_ := fixCtrlVec.last.vecWen.get)
201  io.out.bits.ctrl.fpu.foreach(_ := fixCtrlVec.last.fpu.get)
202  io.out.bits.ctrl.vpu.foreach(_ := fixCtrlVec.last.vpu.get)
203  io.out.bits.perfDebugInfo := fixPerfVec.last
204
205  // vstart illegal
206  if (cfg.exceptionOut.nonEmpty) {
207    val outVstart = fixCtrlVec.last.vpu.get.vstart
208    val vstartIllegal = outVstart =/= 0.U
209    io.out.bits.ctrl.exceptionVec.get := 0.U.asTypeOf(io.out.bits.ctrl.exceptionVec.get)
210    io.out.bits.ctrl.exceptionVec.get(illegalInstr) := vstartIllegal
211  }
212
213  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
214
215  def PipelineReg[TT <: Data](i: Int)(next: TT) = {
216    val lat = preLat min i
217    RegEnable(
218      next,
219      regEnable(lat)
220    )
221  }
222
223  def SNReg[TT <: Data](in: TT, n: Int): TT ={
224    val lat = preLat min n
225    var next = in
226    for (i <- 1 to lat) {
227      next = PipelineReg[TT](i)(next)
228    }
229    next
230  }
231
232  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
233
234  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
235
236  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
237
238  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
239
240  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
241
242}
243
244abstract class PipedFuncUnit(override val cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
245  with HasPipelineReg {
246  override def latency: Int = cfg.latency.latencyVal.get
247}
248