1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).max 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).max 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).max 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).max 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).max 86 def numSrc : Int = srcData.map(_.length).max 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).max 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 /** 167 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 168 * @param data [[DataConfig]] 169 * @param tips tips if get failed 170 * @return the index of special src data 171 */ 172 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 173 val srcIdxVec = srcData.map(x => x.indexOf(data)) 174 val idx0 = srcIdxVec.head 175 for (idx <- srcIdxVec) { 176 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 177 } 178 idx0 179 } 180 181 override def toString: String = { 182 var str = s"${this.name}: " 183 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 184 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 185 str += s"latency($latency)" 186 str 187 } 188} 189 190object FuConfig { 191 val JmpCfg: FuConfig = FuConfig ( 192 name = "jmp", 193 fuType = FuType.jmp, 194 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 195 srcData = Seq( 196 Seq(IntData()), // jal 197 ), 198 piped = true, 199 writeIntRf = true, 200 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 201 ) 202 203 val BrhCfg: FuConfig = FuConfig ( 204 name = "brh", 205 fuType = FuType.brh, 206 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 207 srcData = Seq( 208 Seq(IntData(), IntData()), 209 ), 210 piped = true, 211 immType = Set(SelImm.IMM_SB), 212 ) 213 214 val I2fCfg: FuConfig = FuConfig ( 215 name = "i2f", 216 FuType.i2f, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 218 srcData = Seq( 219 Seq(IntData()), 220 ), 221 piped = true, 222 writeFpRf = true, 223 writeFflags = true, 224 latency = CertainLatency(2), 225 needSrcFrm = true, 226 ) 227 228 val I2vCfg: FuConfig = FuConfig ( 229 name = "i2v", 230 FuType.i2v, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 232 srcData = Seq( 233 Seq(IntData(), IntData()), 234 ), 235 piped = true, 236 writeVecRf = true, 237 latency = CertainLatency(1), 238 dataBits = 128, 239 ) 240 241 val CsrCfg: FuConfig = FuConfig ( 242 name = "csr", 243 fuType = FuType.csr, 244 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 245 srcData = Seq( 246 Seq(IntData()), 247 ), 248 piped = true, 249 writeIntRf = true, 250 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 251 flushPipe = true, 252 ) 253 254 val AluCfg: FuConfig = FuConfig ( 255 name = "alu", 256 fuType = FuType.alu, 257 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 258 srcData = Seq( 259 Seq(IntData(), IntData()), 260 ), 261 piped = true, 262 writeIntRf = true, 263 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 264 ) 265 266 val MulCfg: FuConfig = FuConfig ( 267 name = "mul", 268 fuType = FuType.mul, 269 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 270 srcData = Seq( 271 Seq(IntData(), IntData()), 272 ), 273 piped = true, 274 writeIntRf = true, 275 latency = CertainLatency(2), 276 ) 277 278 val DivCfg: FuConfig = FuConfig ( 279 name = "div", 280 fuType = FuType.div, 281 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 282 srcData = Seq( 283 Seq(IntData(), IntData()), 284 ), 285 piped = false, 286 writeIntRf = true, 287 latency = UncertainLatency(), 288 hasInputBuffer = (true, 4, true) 289 ) 290 291 val FenceCfg: FuConfig = FuConfig ( 292 name = "fence", 293 FuType.fence, 294 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 295 srcData = Seq( 296 Seq(IntData(), IntData()), 297 ), 298 piped = true, 299 latency = CertainLatency(0), 300 exceptionOut = Seq(illegalInstr), 301 flushPipe = true 302 ) 303 304 // Todo: split it to simple bitmap exu and complex bku 305 val BkuCfg: FuConfig = FuConfig ( 306 name = "bku", 307 fuType = FuType.bku, 308 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 309 srcData = Seq( 310 Seq(IntData(), IntData()), 311 ), 312 piped = true, 313 writeIntRf = true, 314 latency = CertainLatency(2), 315 ) 316 317 val VSetRvfWvfCfg: FuConfig = FuConfig( 318 name = "vsetrvfwvf", 319 fuType = FuType.vsetiwf, 320 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 321 srcData = Seq( 322 Seq(FpData(), FpData()), 323 ), 324 piped = true, 325 writeVecRf = true, 326 latency = CertainLatency(0), 327 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 328 ) 329 330 val VSetRiWvfCfg: FuConfig = FuConfig( 331 name = "vsetriwvf", 332 fuType = FuType.vsetiwf, 333 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 334 srcData = Seq( 335 Seq(IntData(), IntData()), 336 ), 337 piped = true, 338 writeVecRf = true, 339 latency = CertainLatency(0), 340 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 341 ) 342 343 val VSetRiWiCfg: FuConfig = FuConfig( 344 name = "vsetriwi", 345 fuType = FuType.vsetiwi, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 347 srcData = Seq( 348 Seq(IntData(), IntData()), 349 ), 350 piped = true, 351 writeIntRf = true, 352 latency = CertainLatency(0), 353 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 354 ) 355 356 val FmacCfg: FuConfig = FuConfig ( 357 name = "fmac", 358 fuType = FuType.fmac, 359 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 360 srcData = Seq( 361 Seq(FpData(), FpData()), 362 Seq(FpData(), FpData(), FpData()), 363 ), 364 piped = false, 365 writeFpRf = true, 366 writeFflags = true, 367 latency = UncertainLatency(), 368 needSrcFrm = true, 369 ) 370 371 val F2iCfg: FuConfig = FuConfig ( 372 name = "f2i", 373 fuType = FuType.fmisc, 374 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 375 srcData = Seq( 376 Seq(FpData(), FpData()), 377 Seq(FpData()), 378 ), 379 piped = true, 380 writeIntRf = true, 381 writeFflags = true, 382 latency = CertainLatency(2), 383 needSrcFrm = true, 384 ) 385 386 val F2fCfg: FuConfig = FuConfig ( 387 name = "f2f", 388 fuType = FuType.fmisc, 389 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 390 srcData = Seq( 391 Seq(FpData(), FpData()), 392 Seq(FpData()), 393 ), 394 piped = true, 395 writeFpRf = true, 396 writeFflags = true, 397 latency = CertainLatency(2), 398 needSrcFrm = true, 399 ) 400 401 val FDivSqrtCfg: FuConfig = FuConfig ( 402 name = "fDivSqrt", 403 fuType = FuType.fDivSqrt, 404 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 405 srcData = Seq( 406 Seq(FpData(), FpData()), 407 ), 408 piped = false, 409 writeFpRf = true, 410 writeFflags = true, 411 latency = UncertainLatency(), 412 hasInputBuffer = (true, 8, true), 413 needSrcFrm = true, 414 ) 415 416 val LduCfg: FuConfig = FuConfig ( 417 name = "ldu", 418 fuType = FuType.ldu, 419 fuGen = null, // Todo 420 srcData = Seq( 421 Seq(IntData()), 422 ), 423 piped = false, // Todo: check it 424 writeIntRf = true, 425 writeFpRf = true, 426 latency = UncertainLatency(3), 427 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 428 flushPipe = true, 429 replayInst = true, 430 hasLoadError = true, 431 immType = Set(SelImm.IMM_I), 432 ) 433 434 val StaCfg: FuConfig = FuConfig ( 435 name = "sta", 436 fuType = FuType.stu, 437 fuGen = null, // Todo 438 srcData = Seq( 439 Seq(IntData()), 440 ), 441 piped = false, 442 latency = UncertainLatency(), 443 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 444 immType = Set(SelImm.IMM_S), 445 ) 446 447 val StdCfg: FuConfig = FuConfig ( 448 name = "std", 449 fuType = FuType.stu, 450 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 451 srcData = Seq( 452 Seq(IntData()), 453 Seq(FpData()), 454 ), 455 piped = true, 456 latency = CertainLatency(0) 457 ) 458 459 val MouCfg: FuConfig = FuConfig ( 460 name = "mou", 461 fuType = FuType.mou, 462 fuGen = null, // Todo 463 srcData = Seq( 464 Seq(IntData()), 465 ), 466 piped = false, // Todo: check it 467 writeIntRf = true, 468 latency = UncertainLatency(), 469 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct 470 ) 471 472 val MoudCfg: FuConfig = FuConfig ( 473 name = "moud", 474 fuType = FuType.mou, 475 fuGen = null, // Todo 476 srcData = Seq( 477 Seq(IntData()), 478 ), 479 piped = true, 480 latency = CertainLatency(0), 481 ) 482 483 val VialuCfg = FuConfig ( 484 name = "vialuFix", 485 fuType = FuType.vialuF, 486 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 487 srcData = Seq( 488 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 489 ), 490 piped = true, 491 writeVecRf = true, 492 writeVxsat = true, 493 latency = CertainLatency(1), 494 vconfigWakeUp = true, 495 maskWakeUp = true, 496 dataBits = 128, 497 exceptionOut = Seq(illegalInstr), 498 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 499 ) 500 501 val VimacCfg = FuConfig ( 502 name = "vimac", 503 fuType = FuType.vimac, 504 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 505 srcData = Seq( 506 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 507 ), 508 piped = true, 509 writeVecRf = true, 510 writeVxsat = true, 511 latency = CertainLatency(2), 512 vconfigWakeUp = true, 513 maskWakeUp = true, 514 dataBits = 128, 515 exceptionOut = Seq(illegalInstr), 516 ) 517 518 val VppuCfg = FuConfig ( 519 name = "vppu", 520 fuType = FuType.vppu, 521 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 522 srcData = Seq( 523 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 524 ), 525 piped = true, 526 writeVecRf = true, 527 writeVxsat = true, 528 latency = CertainLatency(1), 529 vconfigWakeUp = true, 530 maskWakeUp = true, 531 dataBits = 128, 532 exceptionOut = Seq(illegalInstr), 533 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 534 ) 535 536 val VipuCfg: FuConfig = FuConfig ( 537 name = "vipu", 538 fuType = FuType.vipu, 539 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 540 srcData = Seq( 541 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 542 ), 543 piped = true, 544 writeVecRf = true, 545 latency = CertainLatency(1), 546 vconfigWakeUp = true, 547 maskWakeUp = true, 548 dataBits = 128, 549 exceptionOut = Seq(illegalInstr), 550 ) 551 552 val VfaluCfg = FuConfig ( 553 name = "vfalu", 554 fuType = FuType.vfalu, 555 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 556 srcData = Seq( 557 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 558 ), 559 piped = true, 560 writeVecRf = true, 561 writeFpRf = true, 562 writeIntRf = true, 563 writeFflags = true, 564 latency = CertainLatency(1), 565 vconfigWakeUp = true, 566 maskWakeUp = true, 567 dataBits = 128, 568 exceptionOut = Seq(illegalInstr), 569 ) 570 571 val VfmaCfg = FuConfig ( 572 name = "vfma", 573 fuType = FuType.vfma, 574 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 575 srcData = Seq( 576 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 577 ), 578 piped = true, 579 writeVecRf = true, 580 writeFpRf = true, 581 writeFflags = true, 582 latency = CertainLatency(3), 583 vconfigWakeUp = true, 584 maskWakeUp = true, 585 dataBits = 128, 586 exceptionOut = Seq(illegalInstr), 587 ) 588 589 val VfdivCfg = FuConfig( 590 name = "vfdiv", 591 fuType = FuType.vfdiv, 592 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 593 srcData = Seq( 594 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 595 ), 596 piped = false, 597 writeVecRf = true, 598 writeFpRf = true, 599 writeFflags = true, 600 latency = UncertainLatency(), 601 vconfigWakeUp = true, 602 maskWakeUp = true, 603 dataBits = 128, 604 exceptionOut = Seq(illegalInstr), 605 ) 606 607 val VfcvtCfg = FuConfig( 608 name = "vfcvt", 609 fuType = FuType.vfcvt, 610 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 611 srcData = Seq( 612 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 613 ), 614 piped = true, 615 writeVecRf = true, 616 writeFpRf = false, 617 writeFflags = true, 618 latency = CertainLatency(2), 619 vconfigWakeUp = true, 620 maskWakeUp = true, 621 dataBits = 128, 622 exceptionOut = Seq(illegalInstr), 623 ) 624 625 626 val VlduCfg: FuConfig = FuConfig ( 627 name = "vldu", 628 fuType = FuType.vldu, 629 fuGen = null, 630 srcData = Seq( 631 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 632 ), 633 piped = false, // Todo: check it 634 writeVecRf = true, 635 latency = UncertainLatency(), 636 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 637 flushPipe = true, 638 replayInst = true, 639 hasLoadError = true, 640 vconfigWakeUp = true, 641 maskWakeUp = true, 642 dataBits = 128, 643 ) 644 //TODO 645 // def VstuCfg = FuConfig () 646 647 def allConfigs = Seq( 648 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 649 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, 650 VfaluCfg, VfmaCfg 651 ) 652 653 def VecArithFuConfigs = Seq( 654 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 655 ) 656} 657 658