1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 167 fuType == FuType.fmisc || fuType == FuType.div || 168 fuType == FuType.vfdiv 169 170 /** 171 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 172 * @param data [[DataConfig]] 173 * @param tips tips if get failed 174 * @return the index of special src data 175 */ 176 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 177 val srcIdxVec = srcData.map(x => x.indexOf(data)) 178 val idx0 = srcIdxVec.head 179 for (idx <- srcIdxVec) { 180 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 181 } 182 idx0 183 } 184 185 override def toString: String = { 186 var str = s"${this.name}: " 187 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 188 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 189 str += s"latency($latency)" 190 str += s"src($srcData)" 191 str 192 } 193} 194 195object FuConfig { 196 val JmpCfg: FuConfig = FuConfig ( 197 name = "jmp", 198 fuType = FuType.jmp, 199 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 200 srcData = Seq( 201 Seq(IntData()), // jal 202 ), 203 piped = true, 204 writeIntRf = true, 205 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 206 ) 207 208 val BrhCfg: FuConfig = FuConfig ( 209 name = "brh", 210 fuType = FuType.brh, 211 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 212 srcData = Seq( 213 Seq(IntData(), IntData()), 214 ), 215 piped = true, 216 immType = Set(SelImm.IMM_SB), 217 ) 218 219 val I2fCfg: FuConfig = FuConfig ( 220 name = "i2f", 221 FuType.i2f, 222 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 223 srcData = Seq( 224 Seq(IntData()), 225 ), 226 piped = true, 227 writeFpRf = true, 228 writeFflags = true, 229 latency = CertainLatency(2), 230 needSrcFrm = true, 231 ) 232 233 val I2vCfg: FuConfig = FuConfig ( 234 name = "i2v", 235 FuType.i2v, 236 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 237 srcData = Seq( 238 Seq(IntData(), IntData()), 239 ), 240 piped = true, 241 writeVecRf = true, 242 latency = CertainLatency(0), 243 dataBits = 128, 244 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 245 ) 246 247 val CsrCfg: FuConfig = FuConfig ( 248 name = "csr", 249 fuType = FuType.csr, 250 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 251 srcData = Seq( 252 Seq(IntData()), 253 ), 254 piped = true, 255 writeIntRf = true, 256 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 257 flushPipe = true, 258 ) 259 260 val AluCfg: FuConfig = FuConfig ( 261 name = "alu", 262 fuType = FuType.alu, 263 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 264 srcData = Seq( 265 Seq(IntData(), IntData()), 266 ), 267 piped = true, 268 writeIntRf = true, 269 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 270 ) 271 272 val MulCfg: FuConfig = FuConfig ( 273 name = "mul", 274 fuType = FuType.mul, 275 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 276 srcData = Seq( 277 Seq(IntData(), IntData()), 278 ), 279 piped = true, 280 writeIntRf = true, 281 latency = CertainLatency(2), 282 ) 283 284 val DivCfg: FuConfig = FuConfig ( 285 name = "div", 286 fuType = FuType.div, 287 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 288 srcData = Seq( 289 Seq(IntData(), IntData()), 290 ), 291 piped = false, 292 writeIntRf = true, 293 latency = UncertainLatency(), 294 hasInputBuffer = (true, 4, true) 295 ) 296 297 val FenceCfg: FuConfig = FuConfig ( 298 name = "fence", 299 FuType.fence, 300 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 301 srcData = Seq( 302 Seq(IntData(), IntData()), 303 ), 304 piped = true, 305 latency = CertainLatency(0), 306 exceptionOut = Seq(illegalInstr), 307 flushPipe = true 308 ) 309 310 // Todo: split it to simple bitmap exu and complex bku 311 val BkuCfg: FuConfig = FuConfig ( 312 name = "bku", 313 fuType = FuType.bku, 314 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 315 srcData = Seq( 316 Seq(IntData(), IntData()), 317 ), 318 piped = true, 319 writeIntRf = true, 320 latency = CertainLatency(2), 321 ) 322 323 val VSetRvfWvfCfg: FuConfig = FuConfig( 324 name = "vsetrvfwvf", 325 fuType = FuType.vsetfwf, 326 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 327 srcData = Seq( 328 Seq(FpData(), FpData()), 329 ), 330 piped = true, 331 writeVecRf = true, 332 latency = CertainLatency(0), 333 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 334 ) 335 336 val VSetRiWvfCfg: FuConfig = FuConfig( 337 name = "vsetriwvf", 338 fuType = FuType.vsetiwf, 339 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 340 srcData = Seq( 341 Seq(IntData(), IntData()), 342 ), 343 piped = true, 344 writeVecRf = true, 345 latency = CertainLatency(0), 346 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 347 ) 348 349 val VSetRiWiCfg: FuConfig = FuConfig( 350 name = "vsetriwi", 351 fuType = FuType.vsetiwi, 352 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 353 srcData = Seq( 354 Seq(IntData(), IntData()), 355 ), 356 piped = true, 357 writeIntRf = true, 358 latency = CertainLatency(0), 359 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 360 ) 361 362 val FmacCfg: FuConfig = FuConfig ( 363 name = "fmac", 364 fuType = FuType.fmac, 365 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 366 srcData = Seq( 367 Seq(FpData(), FpData()), 368 Seq(FpData(), FpData(), FpData()), 369 ), 370 piped = false, 371 writeFpRf = true, 372 writeFflags = true, 373 latency = UncertainLatency(), 374 needSrcFrm = true, 375 ) 376 377 val F2iCfg: FuConfig = FuConfig ( 378 name = "f2i", 379 fuType = FuType.fmisc, 380 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 381 srcData = Seq( 382 Seq(FpData(), FpData()), 383 Seq(FpData()), 384 ), 385 piped = true, 386 writeIntRf = true, 387 writeFflags = true, 388 latency = CertainLatency(2), 389 needSrcFrm = true, 390 ) 391 392 val F2fCfg: FuConfig = FuConfig ( 393 name = "f2f", 394 fuType = FuType.fmisc, 395 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 396 srcData = Seq( 397 Seq(FpData(), FpData()), 398 Seq(FpData()), 399 ), 400 piped = true, 401 writeFpRf = true, 402 writeFflags = true, 403 latency = CertainLatency(2), 404 needSrcFrm = true, 405 ) 406 407 val FDivSqrtCfg: FuConfig = FuConfig ( 408 name = "fDivSqrt", 409 fuType = FuType.fDivSqrt, 410 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 411 srcData = Seq( 412 Seq(FpData(), FpData()), 413 ), 414 piped = false, 415 writeFpRf = true, 416 writeFflags = true, 417 latency = UncertainLatency(), 418 hasInputBuffer = (true, 8, true), 419 needSrcFrm = true, 420 ) 421 422 val LduCfg: FuConfig = FuConfig ( 423 name = "ldu", 424 fuType = FuType.ldu, 425 fuGen = null, // Todo 426 srcData = Seq( 427 Seq(IntData()), 428 ), 429 piped = false, // Todo: check it 430 writeIntRf = true, 431 writeFpRf = true, 432 latency = UncertainLatency(3), 433 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 434 flushPipe = true, 435 replayInst = true, 436 hasLoadError = true, 437 trigger = true, 438 immType = Set(SelImm.IMM_I), 439 ) 440 441 val StaCfg: FuConfig = FuConfig ( 442 name = "sta", 443 fuType = FuType.stu, 444 fuGen = null, // Todo 445 srcData = Seq( 446 Seq(IntData()), 447 ), 448 piped = false, 449 latency = UncertainLatency(), 450 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 451 trigger = true, 452 immType = Set(SelImm.IMM_S), 453 ) 454 455 val StdCfg: FuConfig = FuConfig ( 456 name = "std", 457 fuType = FuType.stu, 458 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 459 srcData = Seq( 460 Seq(IntData()), 461 Seq(FpData()), 462 ), 463 piped = true, 464 latency = CertainLatency(0) 465 ) 466 467 val HyldaCfg = FuConfig ( 468 name = "hylda", 469 fuType = FuType.ldu, 470 fuGen = null, // Todo 471 srcData = Seq( 472 Seq(IntData()), 473 ), 474 piped = false, // Todo: check it 475 writeIntRf = true, 476 writeFpRf = true, 477 latency = UncertainLatency(3), 478 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 479 flushPipe = true, 480 replayInst = true, 481 hasLoadError = true, 482 immType = Set(SelImm.IMM_I), 483 ) 484 485 val HystaCfg = FuConfig ( 486 name = "hysta", 487 fuType = FuType.stu, 488 fuGen = null, // Todo 489 srcData = Seq( 490 Seq(IntData()), 491 ), 492 piped = false, 493 latency = UncertainLatency(), 494 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 495 immType = Set(SelImm.IMM_S), 496 ) 497 498 val FakeHystaCfg = FuConfig ( 499 name = "hysta", 500 fuType = FuType.stu, 501 fuGen = null, // Todo 502 srcData = Seq(), 503 piped = false, 504 latency = UncertainLatency(), 505 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 506 immType = Set(), 507 ) 508 509 val MouCfg: FuConfig = FuConfig ( 510 name = "mou", 511 fuType = FuType.mou, 512 fuGen = null, // Todo 513 srcData = Seq( 514 Seq(IntData()), 515 ), 516 piped = false, // Todo: check it 517 writeIntRf = true, 518 latency = UncertainLatency(), 519 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 520 trigger = true, 521 ) 522 523 val MoudCfg: FuConfig = FuConfig ( 524 name = "moud", 525 fuType = FuType.mou, 526 fuGen = null, // Todo 527 srcData = Seq( 528 Seq(IntData()), 529 ), 530 piped = true, 531 latency = CertainLatency(0), 532 ) 533 534 val VialuCfg = FuConfig ( 535 name = "vialuFix", 536 fuType = FuType.vialuF, 537 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 538 srcData = Seq( 539 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 540 ), 541 piped = true, 542 writeVecRf = true, 543 writeVxsat = true, 544 latency = CertainLatency(1), 545 vconfigWakeUp = true, 546 maskWakeUp = true, 547 dataBits = 128, 548 exceptionOut = Seq(illegalInstr), 549 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 550 ) 551 552 val VimacCfg = FuConfig ( 553 name = "vimac", 554 fuType = FuType.vimac, 555 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 556 srcData = Seq( 557 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 558 ), 559 piped = true, 560 writeVecRf = true, 561 writeVxsat = true, 562 latency = CertainLatency(2), 563 vconfigWakeUp = true, 564 maskWakeUp = true, 565 dataBits = 128, 566 exceptionOut = Seq(illegalInstr), 567 ) 568 569 val VppuCfg = FuConfig ( 570 name = "vppu", 571 fuType = FuType.vppu, 572 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 573 srcData = Seq( 574 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 575 ), 576 piped = true, 577 writeVecRf = true, 578 writeVxsat = true, 579 latency = CertainLatency(1), 580 vconfigWakeUp = true, 581 maskWakeUp = true, 582 dataBits = 128, 583 exceptionOut = Seq(illegalInstr), 584 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 585 ) 586 587 val VipuCfg: FuConfig = FuConfig ( 588 name = "vipu", 589 fuType = FuType.vipu, 590 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 591 srcData = Seq( 592 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 593 ), 594 piped = true, 595 writeIntRf = true, 596 writeVecRf = true, 597 latency = CertainLatency(1), 598 vconfigWakeUp = true, 599 maskWakeUp = true, 600 dataBits = 128, 601 exceptionOut = Seq(illegalInstr), 602 ) 603 604 val VfaluCfg = FuConfig ( 605 name = "vfalu", 606 fuType = FuType.vfalu, 607 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 608 srcData = Seq( 609 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 610 ), 611 piped = true, 612 writeVecRf = true, 613 writeFpRf = true, 614 writeIntRf = true, 615 writeFflags = true, 616 latency = CertainLatency(1), 617 vconfigWakeUp = true, 618 maskWakeUp = true, 619 dataBits = 128, 620 exceptionOut = Seq(illegalInstr), 621 ) 622 623 val VfmaCfg = FuConfig ( 624 name = "vfma", 625 fuType = FuType.vfma, 626 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 627 srcData = Seq( 628 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 629 ), 630 piped = true, 631 writeVecRf = true, 632 writeFpRf = true, 633 writeFflags = true, 634 latency = CertainLatency(3), 635 vconfigWakeUp = true, 636 maskWakeUp = true, 637 dataBits = 128, 638 exceptionOut = Seq(illegalInstr), 639 ) 640 641 val VfdivCfg = FuConfig( 642 name = "vfdiv", 643 fuType = FuType.vfdiv, 644 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 645 srcData = Seq( 646 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 647 ), 648 piped = false, 649 writeVecRf = true, 650 writeFpRf = true, 651 writeFflags = true, 652 latency = UncertainLatency(), 653 vconfigWakeUp = true, 654 maskWakeUp = true, 655 dataBits = 128, 656 exceptionOut = Seq(illegalInstr), 657 ) 658 659 val VfcvtCfg = FuConfig( 660 name = "vfcvt", 661 fuType = FuType.vfcvt, 662 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 663 srcData = Seq( 664 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 665 ), 666 piped = true, 667 writeVecRf = true, 668 writeFpRf = false, 669 writeFflags = true, 670 latency = CertainLatency(2), 671 vconfigWakeUp = true, 672 maskWakeUp = true, 673 dataBits = 128, 674 exceptionOut = Seq(illegalInstr), 675 ) 676 677 678 val VlduCfg: FuConfig = FuConfig ( 679 name = "vldu", 680 fuType = FuType.vldu, 681 fuGen = null, 682 srcData = Seq( 683 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 684 ), 685 piped = false, // Todo: check it 686 writeVecRf = true, 687 latency = UncertainLatency(), 688 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 689 flushPipe = true, 690 replayInst = true, 691 hasLoadError = true, 692 vconfigWakeUp = true, 693 maskWakeUp = true, 694 dataBits = 128, 695 ) 696 697 val VstuCfg: FuConfig = FuConfig ( 698 name = "vstu", 699 fuType = FuType.vstu, 700 fuGen = null, 701 srcData = Seq( 702 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 703 ), 704 piped = false, 705 writeVecRf = false, 706 latency = UncertainLatency(), 707 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 708 flushPipe = true, 709 replayInst = true, 710 hasLoadError = true, 711 vconfigWakeUp = true, 712 maskWakeUp = true, 713 dataBits = 128, 714 ) 715 716 def allConfigs = Seq( 717 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 718 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 719 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 720 ) 721 722 def VecArithFuConfigs = Seq( 723 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 724 ) 725} 726 727