1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect is in its exception bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf 182 183 def isSta: Boolean = name.contains("sta") 184 185 def ckAlwaysEn: Boolean = isCsr || isFence 186 187 /** 188 * Get index of special src data, like [[VlData]], [[V0Data]] 189 * 190 * @param data [[DataConfig]] 191 * @param tips tips if get failed 192 * @return the index of special src data 193 */ 194 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 195 val srcIdxVec = srcData.map(x => x.indexOf(data)) 196 val idx0 = srcIdxVec.head 197 for (idx <- srcIdxVec) { 198 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 199 } 200 idx0 201 } 202 203 override def toString: String = { 204 var str = s"${this.name}: " 205 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 206 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 207 str += s"latency($latency)" 208 str += s"src($srcData)" 209 str 210 } 211} 212 213object FuConfig { 214 val JmpCfg: FuConfig = FuConfig ( 215 name = "jmp", 216 fuType = FuType.jmp, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 218 srcData = Seq( 219 Seq(IntData()), // jal 220 ), 221 piped = true, 222 writeIntRf = true, 223 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 224 ) 225 226 val BrhCfg: FuConfig = FuConfig ( 227 name = "brh", 228 fuType = FuType.brh, 229 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 230 srcData = Seq( 231 Seq(IntData(), IntData()), 232 ), 233 piped = true, 234 immType = Set(SelImm.IMM_SB), 235 ) 236 237 val I2fCfg: FuConfig = FuConfig ( 238 name = "i2f", 239 FuType.i2f, 240 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 241 srcData = Seq( 242 Seq(IntData()), 243 ), 244 piped = true, 245 writeFpRf = true, 246 writeFflags = true, 247 latency = CertainLatency(2), 248 needSrcFrm = true, 249 ) 250 251 val I2vCfg: FuConfig = FuConfig ( 252 name = "i2v", 253 FuType.i2v, 254 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 255 srcData = Seq( 256 Seq(IntData(), IntData()), 257 ), 258 piped = true, 259 writeFpRf = true, 260 writeVecRf = true, 261 writeV0Rf = true, 262 latency = CertainLatency(0), 263 destDataBits = 128, 264 srcDataBits = Some(64), 265 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 266 ) 267 268 val F2vCfg: FuConfig = FuConfig ( 269 name = "f2v", 270 FuType.f2v, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 272 srcData = Seq( 273 Seq(FpData(), FpData()), 274 Seq(FpData()), 275 ), 276 piped = true, 277 writeVecRf = true, 278 writeV0Rf = true, 279 latency = CertainLatency(0), 280 destDataBits = 128, 281 srcDataBits = Some(64), 282 ) 283 284 val CsrCfg: FuConfig = FuConfig ( 285 name = "csr", 286 fuType = FuType.csr, 287 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 288 srcData = Seq( 289 Seq(IntData()), 290 ), 291 piped = true, 292 writeIntRf = true, 293 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 294 flushPipe = true, 295 ) 296 297 val AluCfg: FuConfig = FuConfig ( 298 name = "alu", 299 fuType = FuType.alu, 300 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 301 srcData = Seq( 302 Seq(IntData(), IntData()), 303 ), 304 piped = true, 305 writeIntRf = true, 306 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 307 ) 308 309 val MulCfg: FuConfig = FuConfig ( 310 name = "mul", 311 fuType = FuType.mul, 312 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 313 srcData = Seq( 314 Seq(IntData(), IntData()), 315 ), 316 piped = true, 317 writeIntRf = true, 318 latency = CertainLatency(2), 319 ) 320 321 val DivCfg: FuConfig = FuConfig ( 322 name = "div", 323 fuType = FuType.div, 324 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 325 srcData = Seq( 326 Seq(IntData(), IntData()), 327 ), 328 piped = false, 329 writeIntRf = true, 330 latency = UncertainLatency(), 331 hasInputBuffer = (true, 4, true) 332 ) 333 334 val FenceCfg: FuConfig = FuConfig ( 335 name = "fence", 336 FuType.fence, 337 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 338 srcData = Seq( 339 Seq(IntData(), IntData()), 340 ), 341 piped = true, 342 latency = CertainLatency(0), 343 exceptionOut = Seq(illegalInstr, virtualInstr), 344 flushPipe = true 345 ) 346 347 // Todo: split it to simple bitmap exu and complex bku 348 val BkuCfg: FuConfig = FuConfig ( 349 name = "bku", 350 fuType = FuType.bku, 351 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 352 srcData = Seq( 353 Seq(IntData(), IntData()), 354 ), 355 piped = true, 356 writeIntRf = true, 357 latency = CertainLatency(2), 358 ) 359 360 val VSetRvfWvfCfg: FuConfig = FuConfig( 361 name = "vsetrvfwvf", 362 fuType = FuType.vsetfwf, 363 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 364 srcData = Seq( 365 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 366 ), 367 piped = true, 368 writeVlRf = true, 369 writeVType = true, 370 writeIntRf = true, 371 latency = CertainLatency(0), 372 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 373 ) 374 375 val VSetRiWvfCfg: FuConfig = FuConfig( 376 name = "vsetriwvf", 377 fuType = FuType.vsetiwf, 378 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 379 srcData = Seq( 380 Seq(IntData(), IntData()), 381 ), 382 piped = true, 383 writeVlRf = true, 384 writeVType = true, 385 latency = CertainLatency(0), 386 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 387 ) 388 389 val VSetRiWiCfg: FuConfig = FuConfig( 390 name = "vsetriwi", 391 fuType = FuType.vsetiwi, 392 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 393 srcData = Seq( 394 Seq(IntData(), IntData()), 395 ), 396 piped = true, 397 writeIntRf = true, 398 latency = CertainLatency(0), 399 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 400 ) 401 402 val LduCfg: FuConfig = FuConfig ( 403 name = "ldu", 404 fuType = FuType.ldu, 405 fuGen = null, // Todo 406 srcData = Seq( 407 Seq(IntData()), 408 ), 409 piped = false, // Todo: check it 410 writeIntRf = true, 411 writeFpRf = true, 412 latency = UncertainLatency(3), 413 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 414 flushPipe = true, 415 replayInst = true, 416 hasLoadError = true, 417 trigger = true, 418 immType = Set(SelImm.IMM_I), 419 ) 420 421 val StaCfg: FuConfig = FuConfig ( 422 name = "sta", 423 fuType = FuType.stu, 424 fuGen = null, // Todo 425 srcData = Seq( 426 Seq(IntData()), 427 ), 428 piped = false, 429 latency = UncertainLatency(), 430 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 431 trigger = true, 432 immType = Set(SelImm.IMM_S), 433 ) 434 435 val StdCfg: FuConfig = FuConfig ( 436 name = "std", 437 fuType = FuType.stu, 438 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 439 srcData = Seq( 440 Seq(IntData()), 441 Seq(FpData()), 442 ), 443 piped = true, 444 latency = CertainLatency(0) 445 ) 446 447 val HyldaCfg = FuConfig ( 448 name = "hylda", 449 fuType = FuType.ldu, 450 fuGen = null, // Todo 451 srcData = Seq( 452 Seq(IntData()), 453 ), 454 piped = false, // Todo: check it 455 writeIntRf = true, 456 writeFpRf = true, 457 latency = UncertainLatency(3), 458 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 459 flushPipe = true, 460 replayInst = true, 461 hasLoadError = true, 462 immType = Set(SelImm.IMM_I), 463 ) 464 465 val HystaCfg = FuConfig ( 466 name = "hysta", 467 fuType = FuType.stu, 468 fuGen = null, // Todo 469 srcData = Seq( 470 Seq(IntData()), 471 ), 472 piped = false, 473 latency = UncertainLatency(), 474 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 475 immType = Set(SelImm.IMM_S), 476 ) 477 478 val FakeHystaCfg = FuConfig ( 479 name = "hysta", 480 fuType = FuType.stu, 481 fuGen = null, // Todo 482 srcData = Seq(), 483 piped = false, 484 latency = UncertainLatency(), 485 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 486 immType = Set(), 487 ) 488 489 val MouCfg: FuConfig = FuConfig ( 490 name = "mou", 491 fuType = FuType.mou, 492 fuGen = null, // Todo 493 srcData = Seq( 494 Seq(IntData()), 495 ), 496 piped = false, // Todo: check it 497 writeFakeIntRf = true, 498 latency = UncertainLatency(), 499 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 500 trigger = true, 501 ) 502 503 val MoudCfg: FuConfig = FuConfig ( 504 name = "moud", 505 fuType = FuType.mou, 506 fuGen = null, // Todo 507 srcData = Seq( 508 Seq(IntData()), 509 ), 510 piped = true, 511 latency = CertainLatency(0), 512 ) 513 514 val VialuCfg = FuConfig ( 515 name = "vialuFix", 516 fuType = FuType.vialuF, 517 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 518 srcData = Seq( 519 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 520 ), 521 piped = true, 522 writeVecRf = true, 523 writeV0Rf = true, 524 writeVxsat = true, 525 needSrcVxrm = true, 526 latency = CertainLatency(1), 527 vconfigWakeUp = true, 528 maskWakeUp = true, 529 destDataBits = 128, 530 exceptionOut = Seq(illegalInstr), 531 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 532 ) 533 534 val VimacCfg = FuConfig ( 535 name = "vimac", 536 fuType = FuType.vimac, 537 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 538 srcData = Seq( 539 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 540 ), 541 piped = true, 542 writeVecRf = true, 543 writeV0Rf = true, 544 writeVxsat = true, 545 needSrcVxrm = true, 546 latency = CertainLatency(2), 547 vconfigWakeUp = true, 548 maskWakeUp = true, 549 destDataBits = 128, 550 exceptionOut = Seq(illegalInstr), 551 ) 552 553 val VidivCfg = FuConfig ( 554 name = "vidiv", 555 fuType = FuType.vidiv, 556 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 557 srcData = Seq( 558 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 559 ), 560 piped = false, 561 writeVecRf = true, 562 writeV0Rf = true, 563 latency = UncertainLatency(), 564 vconfigWakeUp = true, 565 maskWakeUp = true, 566 destDataBits = 128, 567 exceptionOut = Seq(illegalInstr), 568 ) 569 570 val VppuCfg = FuConfig ( 571 name = "vppu", 572 fuType = FuType.vppu, 573 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 574 srcData = Seq( 575 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 576 ), 577 piped = true, 578 writeVecRf = true, 579 writeV0Rf = true, 580 latency = CertainLatency(2), 581 vconfigWakeUp = true, 582 maskWakeUp = true, 583 destDataBits = 128, 584 exceptionOut = Seq(illegalInstr), 585 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 586 ) 587 588 val VipuCfg: FuConfig = FuConfig ( 589 name = "vipu", 590 fuType = FuType.vipu, 591 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 592 srcData = Seq( 593 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 594 ), 595 piped = true, 596 writeIntRf = true, 597 writeVecRf = true, 598 writeV0Rf = true, 599 latency = CertainLatency(2), 600 vconfigWakeUp = true, 601 maskWakeUp = true, 602 destDataBits = 128, 603 exceptionOut = Seq(illegalInstr), 604 ) 605 606 val VfaluCfg = FuConfig ( 607 name = "vfalu", 608 fuType = FuType.vfalu, 609 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 610 srcData = Seq( 611 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 612 ), 613 piped = true, 614 writeVecRf = true, 615 writeV0Rf = true, 616 writeFpRf = true, 617 writeFflags = true, 618 latency = CertainLatency(1), 619 vconfigWakeUp = true, 620 maskWakeUp = true, 621 destDataBits = 128, 622 exceptionOut = Seq(illegalInstr), 623 needSrcFrm = true, 624 ) 625 626 val VfmaCfg = FuConfig ( 627 name = "vfma", 628 fuType = FuType.vfma, 629 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 630 srcData = Seq( 631 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 632 ), 633 piped = true, 634 writeVecRf = true, 635 writeV0Rf = true, 636 writeFflags = true, 637 latency = CertainLatency(3), 638 vconfigWakeUp = true, 639 maskWakeUp = true, 640 destDataBits = 128, 641 exceptionOut = Seq(illegalInstr), 642 needSrcFrm = true, 643 ) 644 645 val VfdivCfg = FuConfig( 646 name = "vfdiv", 647 fuType = FuType.vfdiv, 648 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 649 srcData = Seq( 650 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 651 ), 652 piped = false, 653 writeVecRf = true, 654 writeV0Rf = true, 655 writeFflags = true, 656 latency = UncertainLatency(), 657 vconfigWakeUp = true, 658 maskWakeUp = true, 659 destDataBits = 128, 660 exceptionOut = Seq(illegalInstr), 661 needSrcFrm = true, 662 ) 663 664 val VfcvtCfg = FuConfig( 665 name = "vfcvt", 666 fuType = FuType.vfcvt, 667 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 668 srcData = Seq( 669 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 670 ), 671 piped = true, 672 writeVecRf = true, 673 writeV0Rf = true, 674 writeFflags = true, 675 latency = CertainLatency(2), 676 vconfigWakeUp = true, 677 maskWakeUp = true, 678 destDataBits = 128, 679 exceptionOut = Seq(illegalInstr), 680 needSrcFrm = true, 681 ) 682 683 val FaluCfg = FuConfig( 684 name = "falu", 685 fuType = FuType.falu, 686 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 687 srcData = Seq( 688 Seq(FpData(), FpData()), 689 ), 690 piped = true, 691 writeFpRf = true, 692 writeIntRf = true, 693 writeFflags = true, 694 latency = CertainLatency(1), 695 destDataBits = 64, 696 needSrcFrm = true, 697 ) 698 699 val FmacCfg = FuConfig( 700 name = "fmac", 701 fuType = FuType.fmac, 702 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 703 srcData = Seq( 704 Seq(FpData(), FpData(), FpData()), 705 ), 706 piped = true, 707 writeFpRf = true, 708 writeFflags = true, 709 latency = CertainLatency(3), 710 destDataBits = 64, 711 needSrcFrm = true, 712 ) 713 714 val FdivCfg = FuConfig( 715 name = "fdiv", 716 fuType = FuType.fDivSqrt, 717 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 718 srcData = Seq( 719 Seq(FpData(), FpData()), 720 ), 721 piped = false, 722 writeFpRf = true, 723 writeFflags = true, 724 latency = UncertainLatency(), 725 destDataBits = 64, 726 needSrcFrm = true, 727 ) 728 729 val FcvtCfg = FuConfig( 730 name = "fcvt", 731 fuType = FuType.fcvt, 732 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 733 srcData = Seq( 734 Seq(FpData()), 735 ), 736 piped = true, 737 writeFpRf = true, 738 writeIntRf = true, 739 writeFflags = true, 740 latency = CertainLatency(2), 741 destDataBits = 64, 742 needSrcFrm = true, 743 ) 744 745 val VlduCfg: FuConfig = FuConfig ( 746 name = "vldu", 747 fuType = FuType.vldu, 748 fuGen = null, 749 srcData = Seq( 750 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 751 ), 752 piped = false, // Todo: check it 753 writeVecRf = true, 754 writeV0Rf = true, 755 latency = UncertainLatency(), 756 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 757 flushPipe = true, 758 replayInst = true, 759 hasLoadError = true, 760 vconfigWakeUp = true, 761 maskWakeUp = true, 762 destDataBits = 128, 763 ) 764 765 val VstuCfg: FuConfig = FuConfig ( 766 name = "vstu", 767 fuType = FuType.vstu, 768 fuGen = null, 769 srcData = Seq( 770 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 771 ), 772 piped = false, 773 latency = UncertainLatency(), 774 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 775 flushPipe = true, 776 replayInst = true, 777 hasLoadError = true, 778 vconfigWakeUp = true, 779 maskWakeUp = true, 780 destDataBits = 128, 781 ) 782 783 val VseglduSeg: FuConfig = FuConfig ( 784 name = "vsegldu", 785 fuType = FuType.vsegldu, 786 fuGen = null, 787 srcData = Seq( 788 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 789 ), 790 piped = false, // Todo: check it 791 writeVecRf = true, 792 writeV0Rf = true, 793 latency = UncertainLatency(), 794 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 795 flushPipe = true, 796 replayInst = true, 797 hasLoadError = true, 798 vconfigWakeUp = true, 799 maskWakeUp = true, 800 destDataBits = 128, 801 ) 802 803 val VsegstuCfg: FuConfig = FuConfig( 804 name = "vsegstu", 805 fuType = FuType.vsegstu, 806 fuGen = null, 807 srcData = Seq( 808 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 809 ), 810 piped = false, 811 latency = UncertainLatency(), 812 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 813 flushPipe = true, 814 replayInst = true, 815 hasLoadError = true, 816 vconfigWakeUp = true, 817 maskWakeUp = true, 818 destDataBits = 128, 819 ) 820 821 def allConfigs = Seq( 822 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 823 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 824 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 825 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 826 ) 827 828 def VecArithFuConfigs = Seq( 829 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 830 ) 831} 832 833