1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeV0Rf : Boolean = false, 54 writeVlRf : Boolean = false, 55 writeFakeIntRf: Boolean = false, 56 writeFflags : Boolean = false, 57 writeVxsat : Boolean = false, 58 dataBits : Int = 64, 59 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 60 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 61 exceptionOut : Seq[Int] = Seq(), 62 hasLoadError : Boolean = false, 63 flushPipe : Boolean = false, 64 replayInst : Boolean = false, 65 trigger : Boolean = false, 66 needSrcFrm : Boolean = false, 67 needSrcVxrm : Boolean = false, 68 writeVConfig : Boolean = false, 69 writeVType : Boolean = false, 70 immType : Set[UInt] = Set(), 71 // vector 72 vconfigWakeUp : Boolean = false, 73 maskWakeUp : Boolean = false, 74) { 75 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 76 def needFpWen: Boolean = writeFpRf 77 def needVecWen: Boolean = writeVecRf 78 def needV0Wen: Boolean = writeV0Rf 79 def needVlWen: Boolean = writeVlRf 80 var vconfigIdx = -1 81 var maskSrcIdx = -1 82 if (vconfigWakeUp) { 83 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 84 } 85 if (maskWakeUp) { 86 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 87 } 88 89 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 90 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 91 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 92 93 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 94 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 95 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 96 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 101 102 def readFp: Boolean = numFpSrc > 0 103 104 def fuSel(uop: ExuInput): Bool = { 105 // Don't add more shit here!!! 106 // Todo: add new FuType to distinguish f2i, f2f 107 uop.fuType === this.fuType.U 108 } 109 110 /** 111 * params(i): data type set of the ith src port 112 * @return 113 */ 114 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 115 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 116 // make srcData is uniform sized to avoid exception when transpose 117 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 118 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 119 } 120 121 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 122 srcData 123 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 124 .filter(_.nonEmpty) 125 .map(_.get) 126 .toSet 127 } 128 129 def hasNoDataWB: Boolean = { 130 !(writeIntRf || writeFpRf || writeVecRf) 131 } 132 133 def getSrcMaxWidthVec = { 134 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 135 } 136 137 def genSrcDataVec: Seq[UInt] = { 138 getSrcMaxWidthVec.map(w => UInt(w.W)) 139 } 140 141 // csr's redirect is in its exception bundle 142 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 143 144 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 145 146 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 147 148 // predict info 149 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 152 153 def needFPUCtrl: Boolean = { 154 import FuType._ 155 Seq(fmac, fDivSqrt, i2f).contains(fuType) 156 } 157 158 def needVecCtrl: Boolean = { 159 import FuType._ 160 Seq(falu, fmac, fDivSqrt, fcvt, 161 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 162 } 163 164 def isMul: Boolean = fuType == FuType.mul 165 166 def isDiv: Boolean = fuType == FuType.div 167 168 def isCsr: Boolean = fuType == FuType.csr 169 170 def isFence: Boolean = fuType == FuType.fence 171 172 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 173 fuType == FuType.vppu || fuType == FuType.vipu || 174 fuType == FuType.vfalu || fuType == FuType.vfma || 175 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 176 fuType == FuType.vidiv 177 178 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 179 180 def isSta: Boolean = name.contains("sta") 181 182 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 183 fuType == FuType.div || fuType == FuType.fDivSqrt || 184 fuType == FuType.vfdiv || fuType == FuType.vidiv 185 186 /** 187 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 188 * @param data [[DataConfig]] 189 * @param tips tips if get failed 190 * @return the index of special src data 191 */ 192 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 193 val srcIdxVec = srcData.map(x => x.indexOf(data)) 194 val idx0 = srcIdxVec.head 195 for (idx <- srcIdxVec) { 196 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 197 } 198 idx0 199 } 200 201 override def toString: String = { 202 var str = s"${this.name}: " 203 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 204 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 205 str += s"latency($latency)" 206 str += s"src($srcData)" 207 str 208 } 209} 210 211object FuConfig { 212 val JmpCfg: FuConfig = FuConfig ( 213 name = "jmp", 214 fuType = FuType.jmp, 215 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 216 srcData = Seq( 217 Seq(IntData()), // jal 218 ), 219 piped = true, 220 writeIntRf = true, 221 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 222 ) 223 224 val BrhCfg: FuConfig = FuConfig ( 225 name = "brh", 226 fuType = FuType.brh, 227 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 228 srcData = Seq( 229 Seq(IntData(), IntData()), 230 ), 231 piped = true, 232 immType = Set(SelImm.IMM_SB), 233 ) 234 235 val I2fCfg: FuConfig = FuConfig ( 236 name = "i2f", 237 FuType.i2f, 238 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 239 srcData = Seq( 240 Seq(IntData()), 241 ), 242 piped = true, 243 writeFpRf = true, 244 writeFflags = true, 245 latency = CertainLatency(2), 246 needSrcFrm = true, 247 ) 248 249 val I2vCfg: FuConfig = FuConfig ( 250 name = "i2v", 251 FuType.i2v, 252 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 253 srcData = Seq( 254 Seq(IntData(), IntData()), 255 ), 256 piped = true, 257 writeFpRf = true, 258 writeVecRf = true, 259 latency = CertainLatency(0), 260 dataBits = 128, 261 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 262 ) 263 264 val F2vCfg: FuConfig = FuConfig ( 265 name = "f2v", 266 FuType.f2v, 267 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 268 srcData = Seq( 269 Seq(FpData(), FpData()), 270 Seq(FpData()), 271 ), 272 piped = true, 273 writeVecRf = true, 274 latency = CertainLatency(0), 275 dataBits = 128, 276 ) 277 278 val CsrCfg: FuConfig = FuConfig ( 279 name = "csr", 280 fuType = FuType.csr, 281 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 282 srcData = Seq( 283 Seq(IntData()), 284 ), 285 piped = true, 286 writeIntRf = true, 287 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 288 flushPipe = true, 289 ) 290 291 val AluCfg: FuConfig = FuConfig ( 292 name = "alu", 293 fuType = FuType.alu, 294 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 295 srcData = Seq( 296 Seq(IntData(), IntData()), 297 ), 298 piped = true, 299 writeIntRf = true, 300 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 301 ) 302 303 val MulCfg: FuConfig = FuConfig ( 304 name = "mul", 305 fuType = FuType.mul, 306 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 307 srcData = Seq( 308 Seq(IntData(), IntData()), 309 ), 310 piped = true, 311 writeIntRf = true, 312 latency = CertainLatency(2), 313 ) 314 315 val DivCfg: FuConfig = FuConfig ( 316 name = "div", 317 fuType = FuType.div, 318 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 319 srcData = Seq( 320 Seq(IntData(), IntData()), 321 ), 322 piped = false, 323 writeIntRf = true, 324 latency = UncertainLatency(), 325 hasInputBuffer = (true, 4, true) 326 ) 327 328 val FenceCfg: FuConfig = FuConfig ( 329 name = "fence", 330 FuType.fence, 331 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 332 srcData = Seq( 333 Seq(IntData(), IntData()), 334 ), 335 piped = true, 336 latency = CertainLatency(0), 337 exceptionOut = Seq(illegalInstr, virtualInstr), 338 flushPipe = true 339 ) 340 341 // Todo: split it to simple bitmap exu and complex bku 342 val BkuCfg: FuConfig = FuConfig ( 343 name = "bku", 344 fuType = FuType.bku, 345 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 346 srcData = Seq( 347 Seq(IntData(), IntData()), 348 ), 349 piped = true, 350 writeIntRf = true, 351 latency = CertainLatency(2), 352 ) 353 354 val VSetRvfWvfCfg: FuConfig = FuConfig( 355 name = "vsetrvfwvf", 356 fuType = FuType.vsetfwf, 357 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 358 srcData = Seq( 359 Seq(VecData(), VecData()), 360 ), 361 piped = true, 362 writeVecRf = true, 363 writeVConfig = true, 364 writeVType = true, 365 latency = CertainLatency(0), 366 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 367 ) 368 369 val VSetRiWvfCfg: FuConfig = FuConfig( 370 name = "vsetriwvf", 371 fuType = FuType.vsetiwf, 372 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 373 srcData = Seq( 374 Seq(IntData(), IntData()), 375 ), 376 piped = true, 377 writeVecRf = true, 378 writeVConfig = true, 379 writeVType = true, 380 latency = CertainLatency(0), 381 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 382 ) 383 384 val VSetRiWiCfg: FuConfig = FuConfig( 385 name = "vsetriwi", 386 fuType = FuType.vsetiwi, 387 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 388 srcData = Seq( 389 Seq(IntData(), IntData()), 390 ), 391 piped = true, 392 writeIntRf = true, 393 latency = CertainLatency(0), 394 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 395 ) 396 397 val LduCfg: FuConfig = FuConfig ( 398 name = "ldu", 399 fuType = FuType.ldu, 400 fuGen = null, // Todo 401 srcData = Seq( 402 Seq(IntData()), 403 ), 404 piped = false, // Todo: check it 405 writeIntRf = true, 406 writeFpRf = true, 407 latency = UncertainLatency(3), 408 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 409 flushPipe = true, 410 replayInst = true, 411 hasLoadError = true, 412 trigger = true, 413 immType = Set(SelImm.IMM_I), 414 ) 415 416 val StaCfg: FuConfig = FuConfig ( 417 name = "sta", 418 fuType = FuType.stu, 419 fuGen = null, // Todo 420 srcData = Seq( 421 Seq(IntData()), 422 ), 423 piped = false, 424 latency = UncertainLatency(), 425 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 426 trigger = true, 427 immType = Set(SelImm.IMM_S), 428 ) 429 430 val StdCfg: FuConfig = FuConfig ( 431 name = "std", 432 fuType = FuType.stu, 433 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 434 srcData = Seq( 435 Seq(IntData()), 436 Seq(FpData()), 437 ), 438 piped = true, 439 latency = CertainLatency(0) 440 ) 441 442 val HyldaCfg = FuConfig ( 443 name = "hylda", 444 fuType = FuType.ldu, 445 fuGen = null, // Todo 446 srcData = Seq( 447 Seq(IntData()), 448 ), 449 piped = false, // Todo: check it 450 writeIntRf = true, 451 writeFpRf = true, 452 latency = UncertainLatency(3), 453 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 454 flushPipe = true, 455 replayInst = true, 456 hasLoadError = true, 457 immType = Set(SelImm.IMM_I), 458 ) 459 460 val HystaCfg = FuConfig ( 461 name = "hysta", 462 fuType = FuType.stu, 463 fuGen = null, // Todo 464 srcData = Seq( 465 Seq(IntData()), 466 ), 467 piped = false, 468 latency = UncertainLatency(), 469 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 470 immType = Set(SelImm.IMM_S), 471 ) 472 473 val FakeHystaCfg = FuConfig ( 474 name = "hysta", 475 fuType = FuType.stu, 476 fuGen = null, // Todo 477 srcData = Seq(), 478 piped = false, 479 latency = UncertainLatency(), 480 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 481 immType = Set(), 482 ) 483 484 val MouCfg: FuConfig = FuConfig ( 485 name = "mou", 486 fuType = FuType.mou, 487 fuGen = null, // Todo 488 srcData = Seq( 489 Seq(IntData()), 490 ), 491 piped = false, // Todo: check it 492 writeFakeIntRf = true, 493 latency = UncertainLatency(), 494 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 495 trigger = true, 496 ) 497 498 val MoudCfg: FuConfig = FuConfig ( 499 name = "moud", 500 fuType = FuType.mou, 501 fuGen = null, // Todo 502 srcData = Seq( 503 Seq(IntData()), 504 ), 505 piped = true, 506 latency = CertainLatency(0), 507 ) 508 509 val VialuCfg = FuConfig ( 510 name = "vialuFix", 511 fuType = FuType.vialuF, 512 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 513 srcData = Seq( 514 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 515 ), 516 piped = true, 517 writeVecRf = true, 518 writeVxsat = true, 519 needSrcVxrm = true, 520 latency = CertainLatency(1), 521 vconfigWakeUp = true, 522 maskWakeUp = true, 523 dataBits = 128, 524 exceptionOut = Seq(illegalInstr), 525 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 526 ) 527 528 val VimacCfg = FuConfig ( 529 name = "vimac", 530 fuType = FuType.vimac, 531 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 532 srcData = Seq( 533 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 534 ), 535 piped = true, 536 writeVecRf = true, 537 writeVxsat = true, 538 needSrcVxrm = true, 539 latency = CertainLatency(2), 540 vconfigWakeUp = true, 541 maskWakeUp = true, 542 dataBits = 128, 543 exceptionOut = Seq(illegalInstr), 544 ) 545 546 val VidivCfg = FuConfig ( 547 name = "vidiv", 548 fuType = FuType.vidiv, 549 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 550 srcData = Seq( 551 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 552 ), 553 piped = false, 554 writeVecRf = true, 555 latency = UncertainLatency(), 556 vconfigWakeUp = true, 557 maskWakeUp = true, 558 dataBits = 128, 559 exceptionOut = Seq(illegalInstr), 560 ) 561 562 val VppuCfg = FuConfig ( 563 name = "vppu", 564 fuType = FuType.vppu, 565 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 566 srcData = Seq( 567 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 568 ), 569 piped = true, 570 writeVecRf = true, 571 latency = CertainLatency(2), 572 vconfigWakeUp = true, 573 maskWakeUp = true, 574 dataBits = 128, 575 exceptionOut = Seq(illegalInstr), 576 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 577 ) 578 579 val VipuCfg: FuConfig = FuConfig ( 580 name = "vipu", 581 fuType = FuType.vipu, 582 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 583 srcData = Seq( 584 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 585 ), 586 piped = true, 587 writeIntRf = true, 588 writeVecRf = true, 589 latency = CertainLatency(2), 590 vconfigWakeUp = true, 591 maskWakeUp = true, 592 dataBits = 128, 593 exceptionOut = Seq(illegalInstr), 594 ) 595 596 val VfaluCfg = FuConfig ( 597 name = "vfalu", 598 fuType = FuType.vfalu, 599 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 600 srcData = Seq( 601 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 602 ), 603 piped = true, 604 writeVecRf = true, 605 writeFpRf = true, 606 writeFflags = true, 607 latency = CertainLatency(1), 608 vconfigWakeUp = true, 609 maskWakeUp = true, 610 dataBits = 128, 611 exceptionOut = Seq(illegalInstr), 612 needSrcFrm = true, 613 ) 614 615 val VfmaCfg = FuConfig ( 616 name = "vfma", 617 fuType = FuType.vfma, 618 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 619 srcData = Seq( 620 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 621 ), 622 piped = true, 623 writeVecRf = true, 624 writeFflags = true, 625 latency = CertainLatency(3), 626 vconfigWakeUp = true, 627 maskWakeUp = true, 628 dataBits = 128, 629 exceptionOut = Seq(illegalInstr), 630 needSrcFrm = true, 631 ) 632 633 val VfdivCfg = FuConfig( 634 name = "vfdiv", 635 fuType = FuType.vfdiv, 636 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 637 srcData = Seq( 638 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 639 ), 640 piped = false, 641 writeVecRf = true, 642 writeFflags = true, 643 latency = UncertainLatency(), 644 vconfigWakeUp = true, 645 maskWakeUp = true, 646 dataBits = 128, 647 exceptionOut = Seq(illegalInstr), 648 needSrcFrm = true, 649 ) 650 651 val VfcvtCfg = FuConfig( 652 name = "vfcvt", 653 fuType = FuType.vfcvt, 654 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 655 srcData = Seq( 656 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 657 ), 658 piped = true, 659 writeVecRf = true, 660 writeFflags = true, 661 latency = CertainLatency(2), 662 vconfigWakeUp = true, 663 maskWakeUp = true, 664 dataBits = 128, 665 exceptionOut = Seq(illegalInstr), 666 needSrcFrm = true, 667 ) 668 669 val FaluCfg = FuConfig( 670 name = "falu", 671 fuType = FuType.falu, 672 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 673 srcData = Seq( 674 Seq(FpData(), FpData()), 675 ), 676 piped = true, 677 writeFpRf = true, 678 writeIntRf = true, 679 writeFflags = true, 680 latency = CertainLatency(1), 681 dataBits = 64, 682 needSrcFrm = true, 683 ) 684 685 val FmacCfg = FuConfig( 686 name = "fmac", 687 fuType = FuType.fmac, 688 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 689 srcData = Seq( 690 Seq(FpData(), FpData(), FpData()), 691 ), 692 piped = true, 693 writeFpRf = true, 694 writeFflags = true, 695 latency = CertainLatency(3), 696 dataBits = 64, 697 needSrcFrm = true, 698 ) 699 700 val FdivCfg = FuConfig( 701 name = "fdiv", 702 fuType = FuType.fDivSqrt, 703 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 704 srcData = Seq( 705 Seq(FpData(), FpData()), 706 ), 707 piped = false, 708 writeFpRf = true, 709 writeFflags = true, 710 latency = UncertainLatency(), 711 dataBits = 64, 712 needSrcFrm = true, 713 ) 714 715 val FcvtCfg = FuConfig( 716 name = "fcvt", 717 fuType = FuType.fcvt, 718 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 719 srcData = Seq( 720 Seq(FpData()), 721 ), 722 piped = true, 723 writeFpRf = true, 724 writeIntRf = true, 725 writeFflags = true, 726 latency = CertainLatency(2), 727 dataBits = 64, 728 needSrcFrm = true, 729 ) 730 731 val VlduCfg: FuConfig = FuConfig ( 732 name = "vldu", 733 fuType = FuType.vldu, 734 fuGen = null, 735 srcData = Seq( 736 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 737 ), 738 piped = false, // Todo: check it 739 writeVecRf = true, 740 latency = UncertainLatency(), 741 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 742 flushPipe = true, 743 replayInst = true, 744 hasLoadError = true, 745 vconfigWakeUp = true, 746 maskWakeUp = true, 747 dataBits = 128, 748 ) 749 750 val VstuCfg: FuConfig = FuConfig ( 751 name = "vstu", 752 fuType = FuType.vstu, 753 fuGen = null, 754 srcData = Seq( 755 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 756 ), 757 piped = false, 758 writeVecRf = false, 759 latency = UncertainLatency(), 760 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 761 flushPipe = true, 762 replayInst = true, 763 hasLoadError = true, 764 vconfigWakeUp = true, 765 maskWakeUp = true, 766 dataBits = 128, 767 ) 768 769 val VseglduSeg: FuConfig = FuConfig ( 770 name = "vsegldu", 771 fuType = FuType.vsegldu, 772 fuGen = null, 773 srcData = Seq( 774 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 775 ), 776 piped = false, // Todo: check it 777 writeVecRf = true, 778 latency = UncertainLatency(), 779 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 780 flushPipe = true, 781 replayInst = true, 782 hasLoadError = true, 783 vconfigWakeUp = true, 784 maskWakeUp = true, 785 dataBits = 128, 786 ) 787 788 val VsegstuCfg: FuConfig = FuConfig( 789 name = "vsegstu", 790 fuType = FuType.vsegstu, 791 fuGen = null, 792 srcData = Seq( 793 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 794 ), 795 piped = false, 796 writeVecRf = false, 797 latency = UncertainLatency(), 798 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 799 flushPipe = true, 800 replayInst = true, 801 hasLoadError = true, 802 vconfigWakeUp = true, 803 maskWakeUp = true, 804 dataBits = 128, 805 ) 806 807 def allConfigs = Seq( 808 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 809 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 810 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 811 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 812 ) 813 814 def VecArithFuConfigs = Seq( 815 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 816 ) 817} 818 819