1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param dataBits the width of data in the $fu 30 * @param latency the latency of instuction executed in the $fu 31 * @param hasInputBuffer if the $fu has input buffer 32 * @param exceptionOut the $fu can produce these exception 33 * @param hasLoadError if the $fu has load error out 34 * @param flushPipe if the instuction executed in the $fu need flush out 35 * @param replayInst if the instuction executed in the $fu can replay in some condition 36 * @param trigger if the $fu need trigger out 37 * @param needSrcFrm if the $fu need float rounding mode signal 38 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 39 * @param immType the immediate type of this $fu 40 * @param vconfigWakeUp 41 * @param maskWakeUp 42 * 43 * @define fu function unit 44 */ 45case class FuConfig ( 46 name : String, 47 fuType : FuType.OHType, 48 fuGen : (Parameters, FuConfig) => FuncUnit, 49 srcData : Seq[Seq[DataConfig]], 50 piped : Boolean, 51 maybeBlock : Boolean = false, 52 writeIntRf : Boolean = false, 53 writeFpRf : Boolean = false, 54 writeVecRf : Boolean = false, 55 writeV0Rf : Boolean = false, 56 writeVlRf : Boolean = false, 57 writeFakeIntRf: Boolean = false, 58 writeFflags : Boolean = false, 59 writeVxsat : Boolean = false, 60 dataBits : Int = 64, 61 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 62 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 63 exceptionOut : Seq[Int] = Seq(), 64 hasLoadError : Boolean = false, 65 flushPipe : Boolean = false, 66 replayInst : Boolean = false, 67 trigger : Boolean = false, 68 needSrcFrm : Boolean = false, 69 needSrcVxrm : Boolean = false, 70 writeVType : Boolean = false, 71 immType : Set[UInt] = Set(), 72 // vector 73 vconfigWakeUp : Boolean = false, 74 maskWakeUp : Boolean = false, 75) { 76 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 77 def needFpWen: Boolean = writeFpRf 78 def needVecWen: Boolean = writeVecRf 79 def needV0Wen: Boolean = writeV0Rf 80 def needVlWen: Boolean = writeVlRf 81 var vconfigIdx = -1 82 var maskSrcIdx = -1 83 if (vconfigWakeUp) { 84 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 85 } 86 if (maskWakeUp) { 87 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 88 } 89 90 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 91 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 92 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 93 94 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 95 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 96 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 102 103 def readFp: Boolean = numFpSrc > 0 104 105 def fuSel(uop: ExuInput): Bool = { 106 // Don't add more shit here!!! 107 // Todo: add new FuType to distinguish f2i, f2f 108 uop.fuType === this.fuType.U 109 } 110 111 /** 112 * params(i): data type set of the ith src port 113 * @return 114 */ 115 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 116 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 117 // make srcData is uniform sized to avoid exception when transpose 118 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 119 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 120 } 121 122 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 123 srcData 124 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 125 .filter(_.nonEmpty) 126 .map(_.get) 127 .toSet 128 } 129 130 def hasNoDataWB: Boolean = { 131 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 132 } 133 134 def getSrcMaxWidthVec = { 135 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 136 } 137 138 def genSrcDataVec: Seq[UInt] = { 139 getSrcMaxWidthVec.map(w => UInt(w.W)) 140 } 141 142 // csr's redirect is in its exception bundle 143 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 144 145 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 146 147 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 148 149 // predict info 150 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 151 152 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 153 154 def needFPUCtrl: Boolean = { 155 import FuType._ 156 Seq(fmac, fDivSqrt, i2f).contains(fuType) 157 } 158 159 def needVecCtrl: Boolean = { 160 import FuType._ 161 Seq(falu, fmac, fDivSqrt, fcvt, 162 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 163 } 164 165 def isMul: Boolean = fuType == FuType.mul 166 167 def isDiv: Boolean = fuType == FuType.div 168 169 def isCsr: Boolean = fuType == FuType.csr 170 171 def isFence: Boolean = fuType == FuType.fence 172 173 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 174 fuType == FuType.vppu || fuType == FuType.vipu || 175 fuType == FuType.vfalu || fuType == FuType.vfma || 176 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 177 fuType == FuType.vidiv 178 179 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 180 181 def isSta: Boolean = name.contains("sta") 182 183 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 184 fuType == FuType.div || fuType == FuType.fDivSqrt || 185 fuType == FuType.vfdiv || fuType == FuType.vidiv 186 187 /** 188 * Get index of special src data, like [[VlData]], [[V0Data]] 189 * 190 * @param data [[DataConfig]] 191 * @param tips tips if get failed 192 * @return the index of special src data 193 */ 194 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 195 val srcIdxVec = srcData.map(x => x.indexOf(data)) 196 val idx0 = srcIdxVec.head 197 for (idx <- srcIdxVec) { 198 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 199 } 200 idx0 201 } 202 203 override def toString: String = { 204 var str = s"${this.name}: " 205 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 206 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 207 str += s"latency($latency)" 208 str += s"src($srcData)" 209 str 210 } 211} 212 213object FuConfig { 214 val JmpCfg: FuConfig = FuConfig ( 215 name = "jmp", 216 fuType = FuType.jmp, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 218 srcData = Seq( 219 Seq(IntData()), // jal 220 ), 221 piped = true, 222 writeIntRf = true, 223 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 224 ) 225 226 val BrhCfg: FuConfig = FuConfig ( 227 name = "brh", 228 fuType = FuType.brh, 229 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 230 srcData = Seq( 231 Seq(IntData(), IntData()), 232 ), 233 piped = true, 234 immType = Set(SelImm.IMM_SB), 235 ) 236 237 val I2fCfg: FuConfig = FuConfig ( 238 name = "i2f", 239 FuType.i2f, 240 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 241 srcData = Seq( 242 Seq(IntData()), 243 ), 244 piped = true, 245 writeFpRf = true, 246 writeFflags = true, 247 latency = CertainLatency(2), 248 needSrcFrm = true, 249 ) 250 251 val I2vCfg: FuConfig = FuConfig ( 252 name = "i2v", 253 FuType.i2v, 254 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 255 srcData = Seq( 256 Seq(IntData(), IntData()), 257 ), 258 piped = true, 259 writeFpRf = true, 260 writeVecRf = true, 261 writeV0Rf = true, 262 latency = CertainLatency(0), 263 dataBits = 128, 264 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 265 ) 266 267 val F2vCfg: FuConfig = FuConfig ( 268 name = "f2v", 269 FuType.f2v, 270 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 271 srcData = Seq( 272 Seq(FpData(), FpData()), 273 Seq(FpData()), 274 ), 275 piped = true, 276 writeVecRf = true, 277 writeV0Rf = true, 278 latency = CertainLatency(0), 279 dataBits = 128, 280 ) 281 282 val CsrCfg: FuConfig = FuConfig ( 283 name = "csr", 284 fuType = FuType.csr, 285 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 286 srcData = Seq( 287 Seq(IntData()), 288 ), 289 piped = true, 290 writeIntRf = true, 291 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 292 flushPipe = true, 293 ) 294 295 val AluCfg: FuConfig = FuConfig ( 296 name = "alu", 297 fuType = FuType.alu, 298 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 299 srcData = Seq( 300 Seq(IntData(), IntData()), 301 ), 302 piped = true, 303 writeIntRf = true, 304 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 305 ) 306 307 val MulCfg: FuConfig = FuConfig ( 308 name = "mul", 309 fuType = FuType.mul, 310 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 311 srcData = Seq( 312 Seq(IntData(), IntData()), 313 ), 314 piped = true, 315 writeIntRf = true, 316 latency = CertainLatency(2), 317 ) 318 319 val DivCfg: FuConfig = FuConfig ( 320 name = "div", 321 fuType = FuType.div, 322 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 323 srcData = Seq( 324 Seq(IntData(), IntData()), 325 ), 326 piped = false, 327 writeIntRf = true, 328 latency = UncertainLatency(), 329 hasInputBuffer = (true, 4, true) 330 ) 331 332 val FenceCfg: FuConfig = FuConfig ( 333 name = "fence", 334 FuType.fence, 335 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 336 srcData = Seq( 337 Seq(IntData(), IntData()), 338 ), 339 piped = true, 340 latency = CertainLatency(0), 341 exceptionOut = Seq(illegalInstr, virtualInstr), 342 flushPipe = true 343 ) 344 345 // Todo: split it to simple bitmap exu and complex bku 346 val BkuCfg: FuConfig = FuConfig ( 347 name = "bku", 348 fuType = FuType.bku, 349 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 350 srcData = Seq( 351 Seq(IntData(), IntData()), 352 ), 353 piped = true, 354 writeIntRf = true, 355 latency = CertainLatency(2), 356 ) 357 358 val VSetRvfWvfCfg: FuConfig = FuConfig( 359 name = "vsetrvfwvf", 360 fuType = FuType.vsetfwf, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 362 srcData = Seq( 363 Seq(VecData(), VecData()), 364 ), 365 piped = true, 366 writeVlRf = true, 367 writeVType = true, 368 latency = CertainLatency(0), 369 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 370 ) 371 372 val VSetRiWvfCfg: FuConfig = FuConfig( 373 name = "vsetriwvf", 374 fuType = FuType.vsetiwf, 375 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 376 srcData = Seq( 377 Seq(IntData(), IntData()), 378 ), 379 piped = true, 380 writeVlRf = true, 381 writeVType = true, 382 latency = CertainLatency(0), 383 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 384 ) 385 386 val VSetRiWiCfg: FuConfig = FuConfig( 387 name = "vsetriwi", 388 fuType = FuType.vsetiwi, 389 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 390 srcData = Seq( 391 Seq(IntData(), IntData()), 392 ), 393 piped = true, 394 writeIntRf = true, 395 latency = CertainLatency(0), 396 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 397 ) 398 399 val LduCfg: FuConfig = FuConfig ( 400 name = "ldu", 401 fuType = FuType.ldu, 402 fuGen = null, // Todo 403 srcData = Seq( 404 Seq(IntData()), 405 ), 406 piped = false, // Todo: check it 407 writeIntRf = true, 408 writeFpRf = true, 409 latency = UncertainLatency(3), 410 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 411 flushPipe = true, 412 replayInst = true, 413 hasLoadError = true, 414 trigger = true, 415 immType = Set(SelImm.IMM_I), 416 ) 417 418 val StaCfg: FuConfig = FuConfig ( 419 name = "sta", 420 fuType = FuType.stu, 421 fuGen = null, // Todo 422 srcData = Seq( 423 Seq(IntData()), 424 ), 425 piped = false, 426 latency = UncertainLatency(), 427 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 428 trigger = true, 429 immType = Set(SelImm.IMM_S), 430 ) 431 432 val StdCfg: FuConfig = FuConfig ( 433 name = "std", 434 fuType = FuType.stu, 435 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 436 srcData = Seq( 437 Seq(IntData()), 438 Seq(FpData()), 439 ), 440 piped = true, 441 latency = CertainLatency(0) 442 ) 443 444 val HyldaCfg = FuConfig ( 445 name = "hylda", 446 fuType = FuType.ldu, 447 fuGen = null, // Todo 448 srcData = Seq( 449 Seq(IntData()), 450 ), 451 piped = false, // Todo: check it 452 writeIntRf = true, 453 writeFpRf = true, 454 latency = UncertainLatency(3), 455 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 456 flushPipe = true, 457 replayInst = true, 458 hasLoadError = true, 459 immType = Set(SelImm.IMM_I), 460 ) 461 462 val HystaCfg = FuConfig ( 463 name = "hysta", 464 fuType = FuType.stu, 465 fuGen = null, // Todo 466 srcData = Seq( 467 Seq(IntData()), 468 ), 469 piped = false, 470 latency = UncertainLatency(), 471 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 472 immType = Set(SelImm.IMM_S), 473 ) 474 475 val FakeHystaCfg = FuConfig ( 476 name = "hysta", 477 fuType = FuType.stu, 478 fuGen = null, // Todo 479 srcData = Seq(), 480 piped = false, 481 latency = UncertainLatency(), 482 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 483 immType = Set(), 484 ) 485 486 val MouCfg: FuConfig = FuConfig ( 487 name = "mou", 488 fuType = FuType.mou, 489 fuGen = null, // Todo 490 srcData = Seq( 491 Seq(IntData()), 492 ), 493 piped = false, // Todo: check it 494 writeFakeIntRf = true, 495 latency = UncertainLatency(), 496 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 497 trigger = true, 498 ) 499 500 val MoudCfg: FuConfig = FuConfig ( 501 name = "moud", 502 fuType = FuType.mou, 503 fuGen = null, // Todo 504 srcData = Seq( 505 Seq(IntData()), 506 ), 507 piped = true, 508 latency = CertainLatency(0), 509 ) 510 511 val VialuCfg = FuConfig ( 512 name = "vialuFix", 513 fuType = FuType.vialuF, 514 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 515 srcData = Seq( 516 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 517 ), 518 piped = true, 519 writeVecRf = true, 520 writeV0Rf = true, 521 writeVxsat = true, 522 needSrcVxrm = true, 523 latency = CertainLatency(1), 524 vconfigWakeUp = true, 525 maskWakeUp = true, 526 dataBits = 128, 527 exceptionOut = Seq(illegalInstr), 528 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 529 ) 530 531 val VimacCfg = FuConfig ( 532 name = "vimac", 533 fuType = FuType.vimac, 534 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 535 srcData = Seq( 536 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 537 ), 538 piped = true, 539 writeVecRf = true, 540 writeV0Rf = true, 541 writeVxsat = true, 542 needSrcVxrm = true, 543 latency = CertainLatency(2), 544 vconfigWakeUp = true, 545 maskWakeUp = true, 546 dataBits = 128, 547 exceptionOut = Seq(illegalInstr), 548 ) 549 550 val VidivCfg = FuConfig ( 551 name = "vidiv", 552 fuType = FuType.vidiv, 553 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 554 srcData = Seq( 555 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 556 ), 557 piped = false, 558 writeVecRf = true, 559 writeV0Rf = true, 560 latency = UncertainLatency(), 561 vconfigWakeUp = true, 562 maskWakeUp = true, 563 dataBits = 128, 564 exceptionOut = Seq(illegalInstr), 565 ) 566 567 val VppuCfg = FuConfig ( 568 name = "vppu", 569 fuType = FuType.vppu, 570 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 571 srcData = Seq( 572 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 573 ), 574 piped = true, 575 writeVecRf = true, 576 writeV0Rf = true, 577 latency = CertainLatency(2), 578 vconfigWakeUp = true, 579 maskWakeUp = true, 580 dataBits = 128, 581 exceptionOut = Seq(illegalInstr), 582 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 583 ) 584 585 val VipuCfg: FuConfig = FuConfig ( 586 name = "vipu", 587 fuType = FuType.vipu, 588 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 589 srcData = Seq( 590 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 591 ), 592 piped = true, 593 writeIntRf = true, 594 writeVecRf = true, 595 writeV0Rf = true, 596 latency = CertainLatency(2), 597 vconfigWakeUp = true, 598 maskWakeUp = true, 599 dataBits = 128, 600 exceptionOut = Seq(illegalInstr), 601 ) 602 603 val VfaluCfg = FuConfig ( 604 name = "vfalu", 605 fuType = FuType.vfalu, 606 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 607 srcData = Seq( 608 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 609 ), 610 piped = true, 611 writeVecRf = true, 612 writeV0Rf = true, 613 writeFpRf = true, 614 writeFflags = true, 615 latency = CertainLatency(1), 616 vconfigWakeUp = true, 617 maskWakeUp = true, 618 dataBits = 128, 619 exceptionOut = Seq(illegalInstr), 620 needSrcFrm = true, 621 ) 622 623 val VfmaCfg = FuConfig ( 624 name = "vfma", 625 fuType = FuType.vfma, 626 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 627 srcData = Seq( 628 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 629 ), 630 piped = true, 631 writeVecRf = true, 632 writeV0Rf = true, 633 writeFflags = true, 634 latency = CertainLatency(3), 635 vconfigWakeUp = true, 636 maskWakeUp = true, 637 dataBits = 128, 638 exceptionOut = Seq(illegalInstr), 639 needSrcFrm = true, 640 ) 641 642 val VfdivCfg = FuConfig( 643 name = "vfdiv", 644 fuType = FuType.vfdiv, 645 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 646 srcData = Seq( 647 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 648 ), 649 piped = false, 650 writeVecRf = true, 651 writeV0Rf = true, 652 writeFflags = true, 653 latency = UncertainLatency(), 654 vconfigWakeUp = true, 655 maskWakeUp = true, 656 dataBits = 128, 657 exceptionOut = Seq(illegalInstr), 658 needSrcFrm = true, 659 ) 660 661 val VfcvtCfg = FuConfig( 662 name = "vfcvt", 663 fuType = FuType.vfcvt, 664 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 665 srcData = Seq( 666 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 667 ), 668 piped = true, 669 writeVecRf = true, 670 writeV0Rf = true, 671 writeFflags = true, 672 latency = CertainLatency(2), 673 vconfigWakeUp = true, 674 maskWakeUp = true, 675 dataBits = 128, 676 exceptionOut = Seq(illegalInstr), 677 needSrcFrm = true, 678 ) 679 680 val FaluCfg = FuConfig( 681 name = "falu", 682 fuType = FuType.falu, 683 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 684 srcData = Seq( 685 Seq(FpData(), FpData()), 686 ), 687 piped = true, 688 writeFpRf = true, 689 writeIntRf = true, 690 writeFflags = true, 691 latency = CertainLatency(1), 692 dataBits = 64, 693 needSrcFrm = true, 694 ) 695 696 val FmacCfg = FuConfig( 697 name = "fmac", 698 fuType = FuType.fmac, 699 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 700 srcData = Seq( 701 Seq(FpData(), FpData(), FpData()), 702 ), 703 piped = true, 704 writeFpRf = true, 705 writeFflags = true, 706 latency = CertainLatency(3), 707 dataBits = 64, 708 needSrcFrm = true, 709 ) 710 711 val FdivCfg = FuConfig( 712 name = "fdiv", 713 fuType = FuType.fDivSqrt, 714 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 715 srcData = Seq( 716 Seq(FpData(), FpData()), 717 ), 718 piped = false, 719 writeFpRf = true, 720 writeFflags = true, 721 latency = UncertainLatency(), 722 dataBits = 64, 723 needSrcFrm = true, 724 ) 725 726 val FcvtCfg = FuConfig( 727 name = "fcvt", 728 fuType = FuType.fcvt, 729 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 730 srcData = Seq( 731 Seq(FpData()), 732 ), 733 piped = true, 734 writeFpRf = true, 735 writeIntRf = true, 736 writeFflags = true, 737 latency = CertainLatency(2), 738 dataBits = 64, 739 needSrcFrm = true, 740 ) 741 742 val VlduCfg: FuConfig = FuConfig ( 743 name = "vldu", 744 fuType = FuType.vldu, 745 fuGen = null, 746 srcData = Seq( 747 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 748 ), 749 piped = false, // Todo: check it 750 writeVecRf = true, 751 writeV0Rf = true, 752 latency = UncertainLatency(), 753 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 754 flushPipe = true, 755 replayInst = true, 756 hasLoadError = true, 757 vconfigWakeUp = true, 758 maskWakeUp = true, 759 dataBits = 128, 760 ) 761 762 val VstuCfg: FuConfig = FuConfig ( 763 name = "vstu", 764 fuType = FuType.vstu, 765 fuGen = null, 766 srcData = Seq( 767 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 768 ), 769 piped = false, 770 latency = UncertainLatency(), 771 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 772 flushPipe = true, 773 replayInst = true, 774 hasLoadError = true, 775 vconfigWakeUp = true, 776 maskWakeUp = true, 777 dataBits = 128, 778 ) 779 780 val VseglduSeg: FuConfig = FuConfig ( 781 name = "vsegldu", 782 fuType = FuType.vsegldu, 783 fuGen = null, 784 srcData = Seq( 785 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 786 ), 787 piped = false, // Todo: check it 788 writeVecRf = true, 789 writeV0Rf = true, 790 latency = UncertainLatency(), 791 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 792 flushPipe = true, 793 replayInst = true, 794 hasLoadError = true, 795 vconfigWakeUp = true, 796 maskWakeUp = true, 797 dataBits = 128, 798 ) 799 800 val VsegstuCfg: FuConfig = FuConfig( 801 name = "vsegstu", 802 fuType = FuType.vsegstu, 803 fuGen = null, 804 srcData = Seq( 805 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 806 ), 807 piped = false, 808 latency = UncertainLatency(), 809 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 810 flushPipe = true, 811 replayInst = true, 812 hasLoadError = true, 813 vconfigWakeUp = true, 814 maskWakeUp = true, 815 dataBits = 128, 816 ) 817 818 def allConfigs = Seq( 819 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 820 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 821 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 822 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 823 ) 824 825 def VecArithFuConfigs = Seq( 826 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 827 ) 828} 829 830