1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 /** 167 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 168 * @param data [[DataConfig]] 169 * @param tips tips if get failed 170 * @return the index of special src data 171 */ 172 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 173 val srcIdxVec = srcData.map(x => x.indexOf(data)) 174 val idx0 = srcIdxVec.head 175 for (idx <- srcIdxVec) { 176 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 177 } 178 idx0 179 } 180 181 override def toString: String = { 182 var str = s"${this.name}: " 183 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 184 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 185 str += s"latency($latency)" 186 str += s"src($srcData)" 187 str 188 } 189} 190 191object FuConfig { 192 val JmpCfg: FuConfig = FuConfig ( 193 name = "jmp", 194 fuType = FuType.jmp, 195 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 196 srcData = Seq( 197 Seq(IntData()), // jal 198 ), 199 piped = true, 200 writeIntRf = true, 201 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 202 ) 203 204 val BrhCfg: FuConfig = FuConfig ( 205 name = "brh", 206 fuType = FuType.brh, 207 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 208 srcData = Seq( 209 Seq(IntData(), IntData()), 210 ), 211 piped = true, 212 immType = Set(SelImm.IMM_SB), 213 ) 214 215 val I2fCfg: FuConfig = FuConfig ( 216 name = "i2f", 217 FuType.i2f, 218 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 219 srcData = Seq( 220 Seq(IntData()), 221 ), 222 piped = true, 223 writeFpRf = true, 224 writeFflags = true, 225 latency = CertainLatency(2), 226 needSrcFrm = true, 227 ) 228 229 val I2vCfg: FuConfig = FuConfig ( 230 name = "i2v", 231 FuType.i2v, 232 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 233 srcData = Seq( 234 Seq(IntData(), IntData()), 235 ), 236 piped = true, 237 writeVecRf = true, 238 latency = CertainLatency(0), 239 dataBits = 128, 240 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 241 ) 242 243 val CsrCfg: FuConfig = FuConfig ( 244 name = "csr", 245 fuType = FuType.csr, 246 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 247 srcData = Seq( 248 Seq(IntData()), 249 ), 250 piped = true, 251 writeIntRf = true, 252 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 253 flushPipe = true, 254 ) 255 256 val AluCfg: FuConfig = FuConfig ( 257 name = "alu", 258 fuType = FuType.alu, 259 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 260 srcData = Seq( 261 Seq(IntData(), IntData()), 262 ), 263 piped = true, 264 writeIntRf = true, 265 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 266 ) 267 268 val MulCfg: FuConfig = FuConfig ( 269 name = "mul", 270 fuType = FuType.mul, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 272 srcData = Seq( 273 Seq(IntData(), IntData()), 274 ), 275 piped = true, 276 writeIntRf = true, 277 latency = CertainLatency(2), 278 ) 279 280 val DivCfg: FuConfig = FuConfig ( 281 name = "div", 282 fuType = FuType.div, 283 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 284 srcData = Seq( 285 Seq(IntData(), IntData()), 286 ), 287 piped = false, 288 writeIntRf = true, 289 latency = UncertainLatency(), 290 hasInputBuffer = (true, 4, true) 291 ) 292 293 val FenceCfg: FuConfig = FuConfig ( 294 name = "fence", 295 FuType.fence, 296 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 297 srcData = Seq( 298 Seq(IntData(), IntData()), 299 ), 300 piped = true, 301 latency = CertainLatency(0), 302 exceptionOut = Seq(illegalInstr), 303 flushPipe = true 304 ) 305 306 // Todo: split it to simple bitmap exu and complex bku 307 val BkuCfg: FuConfig = FuConfig ( 308 name = "bku", 309 fuType = FuType.bku, 310 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 311 srcData = Seq( 312 Seq(IntData(), IntData()), 313 ), 314 piped = true, 315 writeIntRf = true, 316 latency = CertainLatency(2), 317 ) 318 319 val VSetRvfWvfCfg: FuConfig = FuConfig( 320 name = "vsetrvfwvf", 321 fuType = FuType.vsetiwf, 322 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 323 srcData = Seq( 324 Seq(FpData(), FpData()), 325 ), 326 piped = true, 327 writeVecRf = true, 328 latency = CertainLatency(0), 329 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 330 ) 331 332 val VSetRiWvfCfg: FuConfig = FuConfig( 333 name = "vsetriwvf", 334 fuType = FuType.vsetiwf, 335 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 336 srcData = Seq( 337 Seq(IntData(), IntData()), 338 ), 339 piped = true, 340 writeVecRf = true, 341 latency = CertainLatency(0), 342 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 343 ) 344 345 val VSetRiWiCfg: FuConfig = FuConfig( 346 name = "vsetriwi", 347 fuType = FuType.vsetiwi, 348 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 349 srcData = Seq( 350 Seq(IntData(), IntData()), 351 ), 352 piped = true, 353 writeIntRf = true, 354 latency = CertainLatency(0), 355 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 356 ) 357 358 val FmacCfg: FuConfig = FuConfig ( 359 name = "fmac", 360 fuType = FuType.fmac, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 362 srcData = Seq( 363 Seq(FpData(), FpData()), 364 Seq(FpData(), FpData(), FpData()), 365 ), 366 piped = false, 367 writeFpRf = true, 368 writeFflags = true, 369 latency = UncertainLatency(), 370 needSrcFrm = true, 371 ) 372 373 val F2iCfg: FuConfig = FuConfig ( 374 name = "f2i", 375 fuType = FuType.fmisc, 376 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 377 srcData = Seq( 378 Seq(FpData(), FpData()), 379 Seq(FpData()), 380 ), 381 piped = true, 382 writeIntRf = true, 383 writeFflags = true, 384 latency = CertainLatency(2), 385 needSrcFrm = true, 386 ) 387 388 val F2fCfg: FuConfig = FuConfig ( 389 name = "f2f", 390 fuType = FuType.fmisc, 391 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 392 srcData = Seq( 393 Seq(FpData(), FpData()), 394 Seq(FpData()), 395 ), 396 piped = true, 397 writeFpRf = true, 398 writeFflags = true, 399 latency = CertainLatency(2), 400 needSrcFrm = true, 401 ) 402 403 val FDivSqrtCfg: FuConfig = FuConfig ( 404 name = "fDivSqrt", 405 fuType = FuType.fDivSqrt, 406 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 407 srcData = Seq( 408 Seq(FpData(), FpData()), 409 ), 410 piped = false, 411 writeFpRf = true, 412 writeFflags = true, 413 latency = UncertainLatency(), 414 hasInputBuffer = (true, 8, true), 415 needSrcFrm = true, 416 ) 417 418 val LduCfg: FuConfig = FuConfig ( 419 name = "ldu", 420 fuType = FuType.ldu, 421 fuGen = null, // Todo 422 srcData = Seq( 423 Seq(IntData()), 424 ), 425 piped = false, // Todo: check it 426 writeIntRf = true, 427 writeFpRf = true, 428 latency = UncertainLatency(3), 429 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 430 flushPipe = true, 431 replayInst = true, 432 hasLoadError = true, 433 trigger = true, 434 immType = Set(SelImm.IMM_I), 435 ) 436 437 val StaCfg: FuConfig = FuConfig ( 438 name = "sta", 439 fuType = FuType.stu, 440 fuGen = null, // Todo 441 srcData = Seq( 442 Seq(IntData()), 443 ), 444 piped = false, 445 latency = UncertainLatency(), 446 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 447 trigger = true, 448 immType = Set(SelImm.IMM_S), 449 ) 450 451 val StdCfg: FuConfig = FuConfig ( 452 name = "std", 453 fuType = FuType.stu, 454 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 455 srcData = Seq( 456 Seq(IntData()), 457 Seq(FpData()), 458 ), 459 piped = true, 460 latency = CertainLatency(0) 461 ) 462 463 val HyldaCfg = FuConfig ( 464 name = "hylda", 465 fuType = FuType.ldu, 466 fuGen = null, // Todo 467 srcData = Seq( 468 Seq(IntData()), 469 ), 470 piped = false, // Todo: check it 471 writeIntRf = true, 472 writeFpRf = true, 473 latency = UncertainLatency(3), 474 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 475 flushPipe = true, 476 replayInst = true, 477 hasLoadError = true, 478 immType = Set(SelImm.IMM_I), 479 ) 480 481 val HystaCfg = FuConfig ( 482 name = "hysta", 483 fuType = FuType.stu, 484 fuGen = null, // Todo 485 srcData = Seq( 486 Seq(IntData()), 487 ), 488 piped = false, 489 latency = UncertainLatency(), 490 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 491 immType = Set(SelImm.IMM_S), 492 ) 493 494 val FakeHystaCfg = FuConfig ( 495 name = "hysta", 496 fuType = FuType.stu, 497 fuGen = null, // Todo 498 srcData = Seq(), 499 piped = false, 500 latency = UncertainLatency(), 501 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 502 immType = Set(), 503 ) 504 505 val MouCfg: FuConfig = FuConfig ( 506 name = "mou", 507 fuType = FuType.mou, 508 fuGen = null, // Todo 509 srcData = Seq( 510 Seq(IntData()), 511 ), 512 piped = false, // Todo: check it 513 writeIntRf = true, 514 latency = UncertainLatency(), 515 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 516 trigger = true, 517 ) 518 519 val MoudCfg: FuConfig = FuConfig ( 520 name = "moud", 521 fuType = FuType.mou, 522 fuGen = null, // Todo 523 srcData = Seq( 524 Seq(IntData()), 525 ), 526 piped = true, 527 latency = CertainLatency(0), 528 ) 529 530 val VialuCfg = FuConfig ( 531 name = "vialuFix", 532 fuType = FuType.vialuF, 533 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 534 srcData = Seq( 535 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 536 ), 537 piped = true, 538 writeVecRf = true, 539 writeVxsat = true, 540 latency = CertainLatency(1), 541 vconfigWakeUp = true, 542 maskWakeUp = true, 543 dataBits = 128, 544 exceptionOut = Seq(illegalInstr), 545 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 546 ) 547 548 val VimacCfg = FuConfig ( 549 name = "vimac", 550 fuType = FuType.vimac, 551 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 552 srcData = Seq( 553 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 554 ), 555 piped = true, 556 writeVecRf = true, 557 writeVxsat = true, 558 latency = CertainLatency(2), 559 vconfigWakeUp = true, 560 maskWakeUp = true, 561 dataBits = 128, 562 exceptionOut = Seq(illegalInstr), 563 ) 564 565 val VppuCfg = FuConfig ( 566 name = "vppu", 567 fuType = FuType.vppu, 568 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 569 srcData = Seq( 570 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 571 ), 572 piped = true, 573 writeVecRf = true, 574 writeVxsat = true, 575 latency = CertainLatency(1), 576 vconfigWakeUp = true, 577 maskWakeUp = true, 578 dataBits = 128, 579 exceptionOut = Seq(illegalInstr), 580 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 581 ) 582 583 val VipuCfg: FuConfig = FuConfig ( 584 name = "vipu", 585 fuType = FuType.vipu, 586 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 587 srcData = Seq( 588 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 589 ), 590 piped = true, 591 writeVecRf = true, 592 latency = CertainLatency(1), 593 vconfigWakeUp = true, 594 maskWakeUp = true, 595 dataBits = 128, 596 exceptionOut = Seq(illegalInstr), 597 ) 598 599 val VfaluCfg = FuConfig ( 600 name = "vfalu", 601 fuType = FuType.vfalu, 602 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 603 srcData = Seq( 604 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 605 ), 606 piped = true, 607 writeVecRf = true, 608 writeFpRf = true, 609 writeIntRf = true, 610 writeFflags = true, 611 latency = CertainLatency(1), 612 vconfigWakeUp = true, 613 maskWakeUp = true, 614 dataBits = 128, 615 exceptionOut = Seq(illegalInstr), 616 ) 617 618 val VfmaCfg = FuConfig ( 619 name = "vfma", 620 fuType = FuType.vfma, 621 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 622 srcData = Seq( 623 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 624 ), 625 piped = true, 626 writeVecRf = true, 627 writeFpRf = true, 628 writeFflags = true, 629 latency = CertainLatency(3), 630 vconfigWakeUp = true, 631 maskWakeUp = true, 632 dataBits = 128, 633 exceptionOut = Seq(illegalInstr), 634 ) 635 636 val VfdivCfg = FuConfig( 637 name = "vfdiv", 638 fuType = FuType.vfdiv, 639 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 640 srcData = Seq( 641 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 642 ), 643 piped = false, 644 writeVecRf = true, 645 writeFpRf = true, 646 writeFflags = true, 647 latency = UncertainLatency(), 648 vconfigWakeUp = true, 649 maskWakeUp = true, 650 dataBits = 128, 651 exceptionOut = Seq(illegalInstr), 652 ) 653 654 val VfcvtCfg = FuConfig( 655 name = "vfcvt", 656 fuType = FuType.vfcvt, 657 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 658 srcData = Seq( 659 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 660 ), 661 piped = true, 662 writeVecRf = true, 663 writeFpRf = false, 664 writeFflags = true, 665 latency = CertainLatency(2), 666 vconfigWakeUp = true, 667 maskWakeUp = true, 668 dataBits = 128, 669 exceptionOut = Seq(illegalInstr), 670 ) 671 672 673 val VlduCfg: FuConfig = FuConfig ( 674 name = "vldu", 675 fuType = FuType.vldu, 676 fuGen = null, 677 srcData = Seq( 678 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 679 ), 680 piped = false, // Todo: check it 681 writeVecRf = true, 682 latency = UncertainLatency(), 683 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 684 flushPipe = true, 685 replayInst = true, 686 hasLoadError = true, 687 vconfigWakeUp = true, 688 maskWakeUp = true, 689 dataBits = 128, 690 ) 691 692 val VstuCfg: FuConfig = FuConfig ( 693 name = "vstu", 694 fuType = FuType.vstu, 695 fuGen = null, 696 srcData = Seq( 697 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 698 ), 699 piped = false, 700 writeVecRf = false, 701 latency = UncertainLatency(), 702 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 703 flushPipe = true, 704 replayInst = true, 705 hasLoadError = true, 706 vconfigWakeUp = true, 707 maskWakeUp = true, 708 dataBits = 128, 709 ) 710 711 def allConfigs = Seq( 712 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 713 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 714 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 715 ) 716 717 def VecArithFuConfigs = Seq( 718 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 719 ) 720} 721 722