1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFflags : Boolean = false, 54 writeVxsat : Boolean = false, 55 dataBits : Int = 64, 56 latency : HasFuLatency = CertainLatency(0), 57 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 58 exceptionOut : Seq[Int] = Seq(), 59 hasLoadError : Boolean = false, 60 flushPipe : Boolean = false, 61 replayInst : Boolean = false, 62 trigger : Boolean = false, 63 needSrcFrm : Boolean = false, 64 needSrcVxrm : Boolean = false, 65 immType : Set[UInt] = Set(), 66 // vector 67 vconfigWakeUp : Boolean = false, 68 maskWakeUp : Boolean = false, 69) { 70 var vconfigIdx = -1 71 var maskSrcIdx = -1 72 if (vconfigWakeUp) { 73 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 74 } 75 if (maskWakeUp) { 76 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 77 } 78 79 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 80 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 81 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 82 83 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 87 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 88 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 89 90 def readFp: Boolean = numFpSrc > 0 91 92 def fuSel(uop: ExuInput): Bool = { 93 // Don't add more shit here!!! 94 // Todo: add new FuType to distinguish f2i, f2f 95 if (this.fuType == FuType.fmisc) { 96 this.name match { 97 case FuConfig.F2iCfg.name => (uop.fuType === FuType.fmisc.U) && uop.rfWen.get && uop.fuType === this.fuType.U 98 case FuConfig.F2fCfg.name => (uop.fuType === FuType.fmisc.U) && uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 99 } 100 } else { 101 uop.fuType === this.fuType.U 102 } 103 } 104 105 /** 106 * params(i): data type set of the ith src port 107 * @return 108 */ 109 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 110 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 111 // make srcData is uniform sized to avoid exception when transpose 112 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 113 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 114 } 115 116 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 117 srcData 118 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 119 .filter(_.nonEmpty) 120 .map(_.get) 121 .toSet 122 } 123 124 def hasNoDataWB: Boolean = { 125 !(writeIntRf || writeFpRf || writeVecRf) 126 } 127 128 def getSrcMaxWidthVec = { 129 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 130 } 131 132 def genSrcDataVec: Seq[UInt] = { 133 getSrcMaxWidthVec.map(w => UInt(w.W)) 134 } 135 136 // csr's redirect is in its exception bundle 137 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 138 139 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 140 141 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 142 143 // predict info 144 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 145 146 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 147 148 def needFPUCtrl: Boolean = { 149 import FuType._ 150 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 151 } 152 153 def needVecCtrl: Boolean = { 154 import FuType._ 155 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 156 } 157 158 def isMul: Boolean = fuType == FuType.mul 159 160 def isDiv: Boolean = fuType == FuType.div 161 162 def isCsr: Boolean = fuType == FuType.csr 163 164 def isFence: Boolean = fuType == FuType.fence 165 166 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 167 fuType == FuType.vppu || fuType == FuType.vipu || 168 fuType == FuType.vfalu || fuType == FuType.vfma || 169 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 170 fuType == FuType.vidiv 171 172 def isSta: Boolean = name.contains("sta") 173 174 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 175 fuType == FuType.fmisc || fuType == FuType.div || 176 fuType == FuType.vfdiv || fuType == FuType.vidiv 177 178 /** 179 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 180 * @param data [[DataConfig]] 181 * @param tips tips if get failed 182 * @return the index of special src data 183 */ 184 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 185 val srcIdxVec = srcData.map(x => x.indexOf(data)) 186 val idx0 = srcIdxVec.head 187 for (idx <- srcIdxVec) { 188 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 189 } 190 idx0 191 } 192 193 override def toString: String = { 194 var str = s"${this.name}: " 195 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 196 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 197 str += s"latency($latency)" 198 str += s"src($srcData)" 199 str 200 } 201} 202 203object FuConfig { 204 val JmpCfg: FuConfig = FuConfig ( 205 name = "jmp", 206 fuType = FuType.jmp, 207 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 208 srcData = Seq( 209 Seq(IntData()), // jal 210 ), 211 piped = true, 212 writeIntRf = true, 213 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 214 ) 215 216 val BrhCfg: FuConfig = FuConfig ( 217 name = "brh", 218 fuType = FuType.brh, 219 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 220 srcData = Seq( 221 Seq(IntData(), IntData()), 222 ), 223 piped = true, 224 immType = Set(SelImm.IMM_SB), 225 ) 226 227 val I2fCfg: FuConfig = FuConfig ( 228 name = "i2f", 229 FuType.i2f, 230 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 231 srcData = Seq( 232 Seq(IntData()), 233 ), 234 piped = true, 235 writeFpRf = true, 236 writeFflags = true, 237 latency = CertainLatency(2), 238 needSrcFrm = true, 239 ) 240 241 val I2vCfg: FuConfig = FuConfig ( 242 name = "i2v", 243 FuType.i2v, 244 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 245 srcData = Seq( 246 Seq(IntData(), IntData()), 247 ), 248 piped = true, 249 writeVecRf = true, 250 latency = CertainLatency(0), 251 dataBits = 128, 252 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 253 ) 254 255 val F2vCfg: FuConfig = FuConfig ( 256 name = "f2v", 257 FuType.f2v, 258 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 259 srcData = Seq( 260 Seq(FpData(), FpData()), 261 Seq(FpData()), 262 ), 263 piped = true, 264 writeVecRf = true, 265 latency = CertainLatency(0), 266 dataBits = 128, 267 ) 268 269 val CsrCfg: FuConfig = FuConfig ( 270 name = "csr", 271 fuType = FuType.csr, 272 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 273 srcData = Seq( 274 Seq(IntData()), 275 ), 276 piped = true, 277 writeIntRf = true, 278 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 279 flushPipe = true, 280 ) 281 282 val AluCfg: FuConfig = FuConfig ( 283 name = "alu", 284 fuType = FuType.alu, 285 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 286 srcData = Seq( 287 Seq(IntData(), IntData()), 288 ), 289 piped = true, 290 writeIntRf = true, 291 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 292 ) 293 294 val MulCfg: FuConfig = FuConfig ( 295 name = "mul", 296 fuType = FuType.mul, 297 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 298 srcData = Seq( 299 Seq(IntData(), IntData()), 300 ), 301 piped = true, 302 writeIntRf = true, 303 latency = CertainLatency(2), 304 ) 305 306 val DivCfg: FuConfig = FuConfig ( 307 name = "div", 308 fuType = FuType.div, 309 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 310 srcData = Seq( 311 Seq(IntData(), IntData()), 312 ), 313 piped = false, 314 writeIntRf = true, 315 latency = UncertainLatency(), 316 hasInputBuffer = (true, 4, true) 317 ) 318 319 val FenceCfg: FuConfig = FuConfig ( 320 name = "fence", 321 FuType.fence, 322 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 323 srcData = Seq( 324 Seq(IntData(), IntData()), 325 ), 326 piped = true, 327 latency = CertainLatency(0), 328 exceptionOut = Seq(illegalInstr), 329 flushPipe = true 330 ) 331 332 // Todo: split it to simple bitmap exu and complex bku 333 val BkuCfg: FuConfig = FuConfig ( 334 name = "bku", 335 fuType = FuType.bku, 336 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 337 srcData = Seq( 338 Seq(IntData(), IntData()), 339 ), 340 piped = true, 341 writeIntRf = true, 342 latency = CertainLatency(2), 343 ) 344 345 val VSetRvfWvfCfg: FuConfig = FuConfig( 346 name = "vsetrvfwvf", 347 fuType = FuType.vsetfwf, 348 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 349 srcData = Seq( 350 Seq(FpData(), FpData()), 351 ), 352 piped = true, 353 writeVecRf = true, 354 latency = CertainLatency(0), 355 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 356 ) 357 358 val VSetRiWvfCfg: FuConfig = FuConfig( 359 name = "vsetriwvf", 360 fuType = FuType.vsetiwf, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 362 srcData = Seq( 363 Seq(IntData(), IntData()), 364 ), 365 piped = true, 366 writeVecRf = true, 367 latency = CertainLatency(0), 368 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 369 ) 370 371 val VSetRiWiCfg: FuConfig = FuConfig( 372 name = "vsetriwi", 373 fuType = FuType.vsetiwi, 374 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 375 srcData = Seq( 376 Seq(IntData(), IntData()), 377 ), 378 piped = true, 379 writeIntRf = true, 380 latency = CertainLatency(0), 381 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 382 ) 383 384 val FmacCfg: FuConfig = FuConfig ( 385 name = "fmac", 386 fuType = FuType.fmac, 387 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 388 srcData = Seq( 389 Seq(FpData(), FpData()), 390 Seq(FpData(), FpData(), FpData()), 391 ), 392 piped = false, 393 writeFpRf = true, 394 writeFflags = true, 395 latency = UncertainLatency(), 396 needSrcFrm = true, 397 ) 398 399 val F2iCfg: FuConfig = FuConfig ( 400 name = "f2i", 401 fuType = FuType.fmisc, 402 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 403 srcData = Seq( 404 Seq(FpData(), FpData()), 405 Seq(FpData()), 406 ), 407 piped = true, 408 writeIntRf = true, 409 writeFflags = true, 410 latency = CertainLatency(2), 411 needSrcFrm = true, 412 ) 413 414 val F2fCfg: FuConfig = FuConfig ( 415 name = "f2f", 416 fuType = FuType.fmisc, 417 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 418 srcData = Seq( 419 Seq(FpData(), FpData()), 420 Seq(FpData()), 421 ), 422 piped = true, 423 writeFpRf = true, 424 writeFflags = true, 425 latency = CertainLatency(2), 426 needSrcFrm = true, 427 ) 428 429 val FDivSqrtCfg: FuConfig = FuConfig ( 430 name = "fDivSqrt", 431 fuType = FuType.fDivSqrt, 432 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 433 srcData = Seq( 434 Seq(FpData(), FpData()), 435 ), 436 piped = false, 437 writeFpRf = true, 438 writeFflags = true, 439 latency = UncertainLatency(), 440 hasInputBuffer = (true, 8, true), 441 needSrcFrm = true, 442 ) 443 444 val LduCfg: FuConfig = FuConfig ( 445 name = "ldu", 446 fuType = FuType.ldu, 447 fuGen = null, // Todo 448 srcData = Seq( 449 Seq(IntData()), 450 ), 451 piped = false, // Todo: check it 452 writeIntRf = true, 453 writeFpRf = true, 454 latency = UncertainLatency(3), 455 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 456 flushPipe = true, 457 replayInst = true, 458 hasLoadError = true, 459 trigger = true, 460 immType = Set(SelImm.IMM_I), 461 ) 462 463 val StaCfg: FuConfig = FuConfig ( 464 name = "sta", 465 fuType = FuType.stu, 466 fuGen = null, // Todo 467 srcData = Seq( 468 Seq(IntData()), 469 ), 470 piped = false, 471 latency = UncertainLatency(), 472 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 473 trigger = true, 474 immType = Set(SelImm.IMM_S), 475 ) 476 477 val StdCfg: FuConfig = FuConfig ( 478 name = "std", 479 fuType = FuType.stu, 480 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 481 srcData = Seq( 482 Seq(IntData()), 483 Seq(FpData()), 484 ), 485 piped = true, 486 latency = CertainLatency(0) 487 ) 488 489 val HyldaCfg = FuConfig ( 490 name = "hylda", 491 fuType = FuType.ldu, 492 fuGen = null, // Todo 493 srcData = Seq( 494 Seq(IntData()), 495 ), 496 piped = false, // Todo: check it 497 writeIntRf = true, 498 writeFpRf = true, 499 latency = UncertainLatency(3), 500 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 501 flushPipe = true, 502 replayInst = true, 503 hasLoadError = true, 504 immType = Set(SelImm.IMM_I), 505 ) 506 507 val HystaCfg = FuConfig ( 508 name = "hysta", 509 fuType = FuType.stu, 510 fuGen = null, // Todo 511 srcData = Seq( 512 Seq(IntData()), 513 ), 514 piped = false, 515 latency = UncertainLatency(), 516 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 517 immType = Set(SelImm.IMM_S), 518 ) 519 520 val FakeHystaCfg = FuConfig ( 521 name = "hysta", 522 fuType = FuType.stu, 523 fuGen = null, // Todo 524 srcData = Seq(), 525 piped = false, 526 latency = UncertainLatency(), 527 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 528 immType = Set(), 529 ) 530 531 val MouCfg: FuConfig = FuConfig ( 532 name = "mou", 533 fuType = FuType.mou, 534 fuGen = null, // Todo 535 srcData = Seq( 536 Seq(IntData()), 537 ), 538 piped = false, // Todo: check it 539 writeIntRf = true, 540 latency = UncertainLatency(), 541 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 542 trigger = true, 543 ) 544 545 val MoudCfg: FuConfig = FuConfig ( 546 name = "moud", 547 fuType = FuType.mou, 548 fuGen = null, // Todo 549 srcData = Seq( 550 Seq(IntData()), 551 ), 552 piped = true, 553 latency = CertainLatency(0), 554 ) 555 556 val VialuCfg = FuConfig ( 557 name = "vialuFix", 558 fuType = FuType.vialuF, 559 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 560 srcData = Seq( 561 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 562 ), 563 piped = true, 564 writeVecRf = true, 565 writeVxsat = true, 566 needSrcVxrm = true, 567 latency = CertainLatency(1), 568 vconfigWakeUp = true, 569 maskWakeUp = true, 570 dataBits = 128, 571 exceptionOut = Seq(illegalInstr), 572 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 573 ) 574 575 val VimacCfg = FuConfig ( 576 name = "vimac", 577 fuType = FuType.vimac, 578 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 579 srcData = Seq( 580 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 581 ), 582 piped = true, 583 writeVecRf = true, 584 writeVxsat = true, 585 needSrcVxrm = true, 586 latency = CertainLatency(2), 587 vconfigWakeUp = true, 588 maskWakeUp = true, 589 dataBits = 128, 590 exceptionOut = Seq(illegalInstr), 591 ) 592 593 val VidivCfg = FuConfig ( 594 name = "vidiv", 595 fuType = FuType.vidiv, 596 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 597 srcData = Seq( 598 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 599 ), 600 piped = false, 601 writeVecRf = true, 602 latency = UncertainLatency(), 603 vconfigWakeUp = true, 604 maskWakeUp = true, 605 dataBits = 128, 606 exceptionOut = Seq(illegalInstr), 607 ) 608 609 val VppuCfg = FuConfig ( 610 name = "vppu", 611 fuType = FuType.vppu, 612 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 613 srcData = Seq( 614 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 615 ), 616 piped = true, 617 writeVecRf = true, 618 latency = CertainLatency(1), 619 vconfigWakeUp = true, 620 maskWakeUp = true, 621 dataBits = 128, 622 exceptionOut = Seq(illegalInstr), 623 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 624 ) 625 626 val VipuCfg: FuConfig = FuConfig ( 627 name = "vipu", 628 fuType = FuType.vipu, 629 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 630 srcData = Seq( 631 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 632 ), 633 piped = true, 634 writeIntRf = true, 635 writeVecRf = true, 636 latency = CertainLatency(1), 637 vconfigWakeUp = true, 638 maskWakeUp = true, 639 dataBits = 128, 640 exceptionOut = Seq(illegalInstr), 641 ) 642 643 val VfaluCfg = FuConfig ( 644 name = "vfalu", 645 fuType = FuType.vfalu, 646 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 647 srcData = Seq( 648 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 649 ), 650 piped = true, 651 writeVecRf = true, 652 writeFpRf = true, 653 writeIntRf = true, 654 writeFflags = true, 655 latency = CertainLatency(1), 656 vconfigWakeUp = true, 657 maskWakeUp = true, 658 dataBits = 128, 659 exceptionOut = Seq(illegalInstr), 660 ) 661 662 val VfmaCfg = FuConfig ( 663 name = "vfma", 664 fuType = FuType.vfma, 665 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 666 srcData = Seq( 667 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 668 ), 669 piped = true, 670 writeVecRf = true, 671 writeFpRf = true, 672 writeFflags = true, 673 latency = CertainLatency(3), 674 vconfigWakeUp = true, 675 maskWakeUp = true, 676 dataBits = 128, 677 exceptionOut = Seq(illegalInstr), 678 ) 679 680 val VfdivCfg = FuConfig( 681 name = "vfdiv", 682 fuType = FuType.vfdiv, 683 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 684 srcData = Seq( 685 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 686 ), 687 piped = false, 688 writeVecRf = true, 689 writeFpRf = true, 690 writeFflags = true, 691 latency = UncertainLatency(), 692 vconfigWakeUp = true, 693 maskWakeUp = true, 694 dataBits = 128, 695 exceptionOut = Seq(illegalInstr), 696 ) 697 698 val VfcvtCfg = FuConfig( 699 name = "vfcvt", 700 fuType = FuType.vfcvt, 701 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 702 srcData = Seq( 703 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 704 ), 705 piped = true, 706 writeVecRf = true, 707 writeFpRf = false, 708 writeFflags = true, 709 latency = CertainLatency(2), 710 vconfigWakeUp = true, 711 maskWakeUp = true, 712 dataBits = 128, 713 exceptionOut = Seq(illegalInstr), 714 ) 715 716 717 val VlduCfg: FuConfig = FuConfig ( 718 name = "vldu", 719 fuType = FuType.vldu, 720 fuGen = null, 721 srcData = Seq( 722 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 723 ), 724 piped = false, // Todo: check it 725 writeVecRf = true, 726 latency = UncertainLatency(), 727 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 728 flushPipe = true, 729 replayInst = true, 730 hasLoadError = true, 731 vconfigWakeUp = true, 732 maskWakeUp = true, 733 dataBits = 128, 734 ) 735 736 val VstuCfg: FuConfig = FuConfig ( 737 name = "vstu", 738 fuType = FuType.vstu, 739 fuGen = null, 740 srcData = Seq( 741 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 742 ), 743 piped = false, 744 writeVecRf = false, 745 latency = UncertainLatency(), 746 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 747 flushPipe = true, 748 replayInst = true, 749 hasLoadError = true, 750 vconfigWakeUp = true, 751 maskWakeUp = true, 752 dataBits = 128, 753 ) 754 755 def allConfigs = Seq( 756 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 757 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 758 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 759 ) 760 761 def VecArithFuConfigs = Seq( 762 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 763 ) 764} 765 766