1package xiangshan.backend.fu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import xiangshan.ExceptionNO._ 6import xiangshan.SelImm 7import xiangshan.backend.Std 8import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP} 9import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf} 10import xiangshan.backend.Bundles.ExuInput 11import xiangshan.backend.datapath.DataConfig._ 12 13/** 14 * 15 * @param name [[String]] name of fuConfig 16 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 17 * @param fuGen how to create $fu 18 * @param srcData type of src data used by this $fu 19 * @param piped if the $fu is pipelined 20 * @param maybeBlock the $fu need ready signal to block internal pipeline 21 * @param writeIntRf the $fu write int regfiles 22 * @param writeFpRf the $fu write float regfiles 23 * @param writeVecRf the $fu write vector regfiles 24 * @param writeFflags the $fu write fflags csr 25 * @param writeVxsat the $fu write vxsat csr 26 * @param dataBits the width of data in the $fu 27 * @param latency the latency of instuction executed in the $fu 28 * @param hasInputBuffer if the $fu has input buffer 29 * @param exceptionOut the $fu can produce these exception 30 * @param hasLoadError if the $fu has load error out 31 * @param flushPipe if the instuction executed in the $fu need flush out 32 * @param replayInst if the instuction executed in the $fu can replay in some condition 33 * @param trigger if the $fu need trigger out 34 * @param needSrcFrm if the $fu need float rounding mode signal 35 * @param immType the immediate type of this $fu 36 * @param vconfigWakeUp 37 * @param maskWakeUp 38 * 39 * @define fu function unit 40 */ 41case class FuConfig ( 42 name : String, 43 fuType : Int, 44 fuGen : (Parameters, FuConfig) => FuncUnit, 45 srcData : Seq[Seq[DataConfig]], 46 piped : Boolean, 47 maybeBlock : Boolean = false, 48 writeIntRf : Boolean = false, 49 writeFpRf : Boolean = false, 50 writeVecRf : Boolean = false, 51 writeFflags : Boolean = false, 52 writeVxsat : Boolean = false, 53 dataBits : Int = 64, 54 latency : HasFuLatency = CertainLatency(0), 55 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 56 exceptionOut : Seq[Int] = Seq(), 57 hasLoadError : Boolean = false, 58 flushPipe : Boolean = false, 59 replayInst : Boolean = false, 60 trigger : Boolean = false, 61 needSrcFrm : Boolean = false, 62 immType : Set[UInt] = Set(), 63 // vector 64 vconfigWakeUp : Boolean = false, 65 maskWakeUp : Boolean = false, 66) { 67 var vconfigIdx = -1 68 var maskSrcIdx = -1 69 if (vconfigWakeUp) { 70 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 71 } 72 if (maskWakeUp) { 73 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 74 } 75 76 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 77 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 78 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 79 80 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).max 81 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).max 82 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).max 83 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).max 84 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).max 85 def numSrc : Int = srcData.map(_.length).max 86 87 def readFp: Boolean = numFpSrc > 0 88 89 def fuSel(uop: ExuInput): Bool = { 90 // Don't add more shit here!!! 91 // Todo: add new FuType to distinguish f2i, f2f 92 if (this.fuType == FuType.fmisc) { 93 this.name match { 94 case FuConfig.F2iCfg.name => uop.rfWen.get 95 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt 96 } 97 } else { 98 uop.fuType === this.fuType.U 99 } 100 } 101 102 /** 103 * params(i): data type set of the ith src port 104 * @return 105 */ 106 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 107 val numSrcMax = srcData.map(_.length).max 108 // make srcData is uniform sized to avoid exception when transpose 109 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 110 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 111 } 112 113 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 114 srcData 115 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 116 .filter(_.nonEmpty) 117 .map(_.get) 118 .toSet 119 } 120 121 def hasNoDataWB: Boolean = { 122 !(writeIntRf || writeFpRf || writeVecRf) 123 } 124 125 def getSrcMaxWidthVec = { 126 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 127 } 128 129 def genSrcDataVec: Seq[UInt] = { 130 getSrcMaxWidthVec.map(w => UInt(w.W)) 131 } 132 133 // csr's redirect is in its exception bundle 134 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 135 136 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 137 138 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 139 140 def needFPUCtrl: Boolean = { 141 import FuType._ 142 Set(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 143 } 144 145 def needVecCtrl: Boolean = { 146 import FuType._ 147 Set(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv).contains(fuType) 148 } 149 150 def isMul: Boolean = fuType == FuType.mul 151 152 def isDiv: Boolean = fuType == FuType.div 153 154 def isCsr: Boolean = fuType == FuType.csr 155 156 def isFence: Boolean = fuType == FuType.fence 157 158 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 159 fuType == FuType.vppu || fuType == FuType.vipu || 160 fuType == FuType.vfalu || fuType == FuType.vfma || 161 fuType == FuType.vfdiv 162 163 def isSta: Boolean = name.contains("sta") 164 165 /** 166 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 167 * @param data [[DataConfig]] 168 * @param tips tips if get failed 169 * @return the index of special src data 170 */ 171 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 172 val srcIdxVec = srcData.map(x => x.indexOf(data)) 173 val idx0 = srcIdxVec.head 174 for (idx <- srcIdxVec) { 175 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 176 } 177 idx0 178 } 179 180 override def toString: String = { 181 var str = s"${this.name}: " 182 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 183 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 184 str += s"latency($latency)" 185 str 186 } 187} 188 189object FuConfig { 190 val JmpCfg: FuConfig = FuConfig ( 191 name = "jmp", 192 fuType = FuType.jmp, 193 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 194 srcData = Seq( 195 Seq(IntData()), // jal 196 ), 197 piped = true, 198 writeIntRf = true, 199 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 200 ) 201 202 val BrhCfg: FuConfig = FuConfig ( 203 name = "brh", 204 fuType = FuType.brh, 205 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 206 srcData = Seq( 207 Seq(IntData(), IntData()), 208 ), 209 piped = true, 210 immType = Set(SelImm.IMM_SB), 211 ) 212 213 val I2fCfg: FuConfig = FuConfig ( 214 name = "i2f", 215 FuType.i2f, 216 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 217 srcData = Seq( 218 Seq(IntData()), 219 ), 220 piped = true, 221 writeFpRf = true, 222 writeFflags = true, 223 latency = CertainLatency(2), 224 needSrcFrm = true, 225 ) 226 227 val CsrCfg: FuConfig = FuConfig ( 228 name = "csr", 229 fuType = FuType.csr, 230 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 231 srcData = Seq( 232 Seq(IntData()), 233 ), 234 piped = true, 235 writeIntRf = true, 236 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 237 flushPipe = true, 238 ) 239 240 val AluCfg: FuConfig = FuConfig ( 241 name = "alu", 242 fuType = FuType.alu, 243 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 244 srcData = Seq( 245 Seq(IntData(), IntData()), 246 ), 247 piped = true, 248 writeIntRf = true, 249 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 250 ) 251 252 val MulCfg: FuConfig = FuConfig ( 253 name = "mul", 254 fuType = FuType.mul, 255 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 256 srcData = Seq( 257 Seq(IntData(), IntData()), 258 ), 259 piped = true, 260 writeIntRf = true, 261 latency = CertainLatency(2), 262 ) 263 264 val DivCfg: FuConfig = FuConfig ( 265 name = "div", 266 fuType = FuType.div, 267 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 268 srcData = Seq( 269 Seq(IntData(), IntData()), 270 ), 271 piped = false, 272 writeIntRf = true, 273 latency = UncertainLatency(), 274 hasInputBuffer = (true, 4, true) 275 ) 276 277 val FenceCfg: FuConfig = FuConfig ( 278 name = "fence", 279 FuType.fence, 280 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 281 srcData = Seq( 282 Seq(IntData(), IntData()), 283 ), 284 piped = true, 285 latency = CertainLatency(0), 286 exceptionOut = Seq(illegalInstr), 287 flushPipe = true 288 ) 289 290 // Todo: split it to simple bitmap exu and complex bku 291 val BkuCfg: FuConfig = FuConfig ( 292 name = "bku", 293 fuType = FuType.bku, 294 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 295 srcData = Seq( 296 Seq(IntData(), IntData()), 297 ), 298 piped = true, 299 writeIntRf = true, 300 latency = CertainLatency(2), 301 ) 302 303 val VSetRvfWvfCfg: FuConfig = FuConfig( 304 name = "vsetrvfwvf", 305 fuType = FuType.vsetiwf, 306 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 307 srcData = Seq( 308 Seq(FpData(), FpData()), 309 ), 310 piped = true, 311 writeVecRf = true, 312 latency = CertainLatency(0), 313 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 314 ) 315 316 val VSetRiWvfCfg: FuConfig = FuConfig( 317 name = "vsetriwvf", 318 fuType = FuType.vsetiwf, 319 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 320 srcData = Seq( 321 Seq(IntData(), IntData()), 322 ), 323 piped = true, 324 writeVecRf = true, 325 latency = CertainLatency(0), 326 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 327 ) 328 329 val VSetRiWiCfg: FuConfig = FuConfig( 330 name = "vsetriwi", 331 fuType = FuType.vsetiwi, 332 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 333 srcData = Seq( 334 Seq(IntData(), IntData()), 335 ), 336 piped = true, 337 writeIntRf = true, 338 latency = CertainLatency(0), 339 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 340 ) 341 342 val FmacCfg: FuConfig = FuConfig ( 343 name = "fmac", 344 fuType = FuType.fmac, 345 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 346 srcData = Seq( 347 Seq(FpData(), FpData()), 348 Seq(FpData(), FpData(), FpData()), 349 ), 350 piped = false, 351 writeFpRf = true, 352 writeFflags = true, 353 latency = UncertainLatency(), 354 needSrcFrm = true, 355 ) 356 357 val F2iCfg: FuConfig = FuConfig ( 358 name = "f2i", 359 fuType = FuType.fmisc, 360 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 361 srcData = Seq( 362 Seq(FpData(), FpData()), 363 Seq(FpData()), 364 ), 365 piped = true, 366 writeIntRf = true, 367 writeFflags = true, 368 latency = CertainLatency(2), 369 needSrcFrm = true, 370 ) 371 372 val F2fCfg: FuConfig = FuConfig ( 373 name = "f2f", 374 fuType = FuType.fmisc, 375 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 376 srcData = Seq( 377 Seq(FpData(), FpData()), 378 Seq(FpData()), 379 ), 380 piped = true, 381 writeFpRf = true, 382 writeFflags = true, 383 latency = CertainLatency(2), 384 needSrcFrm = true, 385 ) 386 387 val FDivSqrtCfg: FuConfig = FuConfig ( 388 name = "fDivSqrt", 389 fuType = FuType.fDivSqrt, 390 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 391 srcData = Seq( 392 Seq(FpData(), FpData()), 393 ), 394 piped = false, 395 writeFpRf = true, 396 writeFflags = true, 397 latency = UncertainLatency(), 398 hasInputBuffer = (true, 8, true), 399 needSrcFrm = true, 400 ) 401 402 val LduCfg: FuConfig = FuConfig ( 403 name = "ldu", 404 fuType = FuType.ldu, 405 fuGen = null, // Todo 406 srcData = Seq( 407 Seq(IntData()), 408 ), 409 piped = false, // Todo: check it 410 writeIntRf = true, 411 writeFpRf = true, 412 latency = UncertainLatency(3), 413 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 414 flushPipe = true, 415 replayInst = true, 416 hasLoadError = true, 417 immType = Set(SelImm.IMM_I), 418 ) 419 420 val StaCfg: FuConfig = FuConfig ( 421 name = "sta", 422 fuType = FuType.stu, 423 fuGen = null, // Todo 424 srcData = Seq( 425 Seq(IntData()), 426 ), 427 piped = false, 428 latency = UncertainLatency(), 429 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 430 immType = Set(SelImm.IMM_S), 431 ) 432 433 val StdCfg: FuConfig = FuConfig ( 434 name = "std", 435 fuType = FuType.stu, 436 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 437 srcData = Seq( 438 Seq(IntData()), 439 Seq(FpData()), 440 ), 441 piped = true, 442 latency = CertainLatency(0) 443 ) 444 445 val MouCfg: FuConfig = FuConfig ( 446 name = "mou", 447 fuType = FuType.mou, 448 fuGen = null, // Todo 449 srcData = Seq( 450 Seq(IntData()), 451 ), 452 piped = false, // Todo: check it 453 writeIntRf = true, 454 latency = UncertainLatency(), 455 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct 456 ) 457 458 val MoudCfg: FuConfig = FuConfig ( 459 name = "moud", 460 fuType = FuType.mou, 461 fuGen = null, // Todo 462 srcData = Seq( 463 Seq(IntData()), 464 ), 465 piped = true, 466 latency = CertainLatency(0), 467 ) 468 469 val VialuCfg = FuConfig ( 470 name = "vialuFix", 471 fuType = FuType.vialuF, 472 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 473 srcData = Seq( 474 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 475 ), 476 piped = true, 477 writeVecRf = true, 478 writeVxsat = true, 479 latency = CertainLatency(1), 480 vconfigWakeUp = true, 481 maskWakeUp = true, 482 dataBits = 128, 483 exceptionOut = Seq(illegalInstr), 484 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 485 ) 486 487 val VimacCfg = FuConfig ( 488 name = "vimac", 489 fuType = FuType.vimac, 490 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 491 srcData = Seq( 492 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 493 ), 494 piped = true, 495 writeVecRf = true, 496 writeVxsat = true, 497 latency = CertainLatency(2), 498 vconfigWakeUp = true, 499 maskWakeUp = true, 500 dataBits = 128, 501 exceptionOut = Seq(illegalInstr), 502 ) 503 504 val VppuCfg = FuConfig ( 505 name = "vppu", 506 fuType = FuType.vppu, 507 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 508 srcData = Seq( 509 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 510 ), 511 piped = true, 512 writeVecRf = true, 513 writeVxsat = true, 514 latency = CertainLatency(1), 515 vconfigWakeUp = true, 516 maskWakeUp = true, 517 dataBits = 128, 518 exceptionOut = Seq(illegalInstr), 519 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 520 ) 521 522 val VipuCfg: FuConfig = FuConfig ( 523 name = "vipu", 524 fuType = FuType.vipu, 525 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 526 srcData = Seq( 527 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 528 ), 529 piped = true, 530 writeVecRf = true, 531 latency = CertainLatency(1), 532 vconfigWakeUp = true, 533 maskWakeUp = true, 534 dataBits = 128, 535 exceptionOut = Seq(illegalInstr), 536 ) 537 538 val VfaluCfg = FuConfig ( 539 name = "vfalu", 540 fuType = FuType.vfalu, 541 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 542 srcData = Seq( 543 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 544 ), 545 piped = true, 546 writeVecRf = true, 547 writeFpRf = true, 548 writeIntRf = true, 549 writeFflags = true, 550 latency = CertainLatency(1), 551 vconfigWakeUp = true, 552 maskWakeUp = true, 553 dataBits = 128, 554 exceptionOut = Seq(illegalInstr), 555 ) 556 557 val VfmaCfg = FuConfig ( 558 name = "vfma", 559 fuType = FuType.vfma, 560 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 561 srcData = Seq( 562 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 563 ), 564 piped = true, 565 writeVecRf = true, 566 writeFpRf = true, 567 writeFflags = true, 568 latency = CertainLatency(3), 569 vconfigWakeUp = true, 570 maskWakeUp = true, 571 dataBits = 128, 572 exceptionOut = Seq(illegalInstr), 573 ) 574 575 val VfdivCfg = FuConfig( 576 name = "vfdiv", 577 fuType = FuType.vfdiv, 578 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 579 srcData = Seq( 580 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 581 ), 582 piped = false, 583 writeVecRf = true, 584 writeFpRf = true, 585 writeFflags = true, 586 latency = UncertainLatency(), 587 vconfigWakeUp = true, 588 maskWakeUp = true, 589 dataBits = 128, 590 exceptionOut = Seq(illegalInstr), 591 ) 592 593 val VlduCfg: FuConfig = FuConfig ( 594 name = "vldu", 595 fuType = FuType.vldu, 596 fuGen = null, 597 srcData = Seq( 598 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 599 ), 600 piped = false, // Todo: check it 601 writeVecRf = true, 602 latency = UncertainLatency(), 603 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 604 flushPipe = true, 605 replayInst = true, 606 hasLoadError = true, 607 vconfigWakeUp = true, 608 maskWakeUp = true, 609 dataBits = 128, 610 ) 611 //TODO 612 // def VstuCfg = FuConfig () 613 614 def allConfigs = Seq( 615 JmpCfg, BrhCfg, I2fCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 616 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, 617 VfaluCfg, VfmaCfg 618 ) 619 620 def VecArithFuConfigs = Seq( 621 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 622 ) 623} 624 625