1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0), 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 immType : Set[UInt] = Set(), 67 // vector 68 vconfigWakeUp : Boolean = false, 69 maskWakeUp : Boolean = false, 70) { 71 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 72 def needFpWen: Boolean = writeFpRf 73 def needVecWen: Boolean = writeVecRf 74 var vconfigIdx = -1 75 var maskSrcIdx = -1 76 if (vconfigWakeUp) { 77 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 78 } 79 if (maskWakeUp) { 80 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 81 } 82 83 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 84 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 85 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 86 87 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 88 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 93 94 def readFp: Boolean = numFpSrc > 0 95 96 def fuSel(uop: ExuInput): Bool = { 97 // Don't add more shit here!!! 98 // Todo: add new FuType to distinguish f2i, f2f 99 if (this.fuType == FuType.fmisc) { 100 this.name match { 101 case FuConfig.F2iCfg.name => (uop.fuType === FuType.fmisc.U) && uop.rfWen.get && uop.fuType === this.fuType.U 102 case FuConfig.F2fCfg.name => (uop.fuType === FuType.fmisc.U) && uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 103 } 104 } else { 105 uop.fuType === this.fuType.U 106 } 107 } 108 109 /** 110 * params(i): data type set of the ith src port 111 * @return 112 */ 113 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 114 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 115 // make srcData is uniform sized to avoid exception when transpose 116 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 117 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 118 } 119 120 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 121 srcData 122 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 123 .filter(_.nonEmpty) 124 .map(_.get) 125 .toSet 126 } 127 128 def hasNoDataWB: Boolean = { 129 !(writeIntRf || writeFpRf || writeVecRf) 130 } 131 132 def getSrcMaxWidthVec = { 133 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 134 } 135 136 def genSrcDataVec: Seq[UInt] = { 137 getSrcMaxWidthVec.map(w => UInt(w.W)) 138 } 139 140 // csr's redirect is in its exception bundle 141 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 142 143 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 144 145 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 146 147 // predict info 148 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 149 150 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 151 152 def needFPUCtrl: Boolean = { 153 import FuType._ 154 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 155 } 156 157 def needVecCtrl: Boolean = { 158 import FuType._ 159 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 160 } 161 162 def isMul: Boolean = fuType == FuType.mul 163 164 def isDiv: Boolean = fuType == FuType.div 165 166 def isCsr: Boolean = fuType == FuType.csr 167 168 def isFence: Boolean = fuType == FuType.fence 169 170 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 171 fuType == FuType.vppu || fuType == FuType.vipu || 172 fuType == FuType.vfalu || fuType == FuType.vfma || 173 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 174 fuType == FuType.vidiv 175 176 def isSta: Boolean = name.contains("sta") 177 178 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 179 fuType == FuType.fmisc || fuType == FuType.div || 180 fuType == FuType.vfdiv || fuType == FuType.vidiv 181 182 /** 183 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 184 * @param data [[DataConfig]] 185 * @param tips tips if get failed 186 * @return the index of special src data 187 */ 188 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 189 val srcIdxVec = srcData.map(x => x.indexOf(data)) 190 val idx0 = srcIdxVec.head 191 for (idx <- srcIdxVec) { 192 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 193 } 194 idx0 195 } 196 197 override def toString: String = { 198 var str = s"${this.name}: " 199 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 200 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 201 str += s"latency($latency)" 202 str += s"src($srcData)" 203 str 204 } 205} 206 207object FuConfig { 208 val JmpCfg: FuConfig = FuConfig ( 209 name = "jmp", 210 fuType = FuType.jmp, 211 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 212 srcData = Seq( 213 Seq(IntData()), // jal 214 ), 215 piped = true, 216 writeIntRf = true, 217 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 218 ) 219 220 val BrhCfg: FuConfig = FuConfig ( 221 name = "brh", 222 fuType = FuType.brh, 223 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 224 srcData = Seq( 225 Seq(IntData(), IntData()), 226 ), 227 piped = true, 228 immType = Set(SelImm.IMM_SB), 229 ) 230 231 val I2fCfg: FuConfig = FuConfig ( 232 name = "i2f", 233 FuType.i2f, 234 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 235 srcData = Seq( 236 Seq(IntData()), 237 ), 238 piped = true, 239 writeFpRf = true, 240 writeFflags = true, 241 latency = CertainLatency(2), 242 needSrcFrm = true, 243 ) 244 245 val I2vCfg: FuConfig = FuConfig ( 246 name = "i2v", 247 FuType.i2v, 248 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 249 srcData = Seq( 250 Seq(IntData(), IntData()), 251 ), 252 piped = true, 253 writeVecRf = true, 254 latency = CertainLatency(0), 255 dataBits = 128, 256 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 257 ) 258 259 val F2vCfg: FuConfig = FuConfig ( 260 name = "f2v", 261 FuType.f2v, 262 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 263 srcData = Seq( 264 Seq(FpData(), FpData()), 265 Seq(FpData()), 266 ), 267 piped = true, 268 writeVecRf = true, 269 latency = CertainLatency(0), 270 dataBits = 128, 271 ) 272 273 val CsrCfg: FuConfig = FuConfig ( 274 name = "csr", 275 fuType = FuType.csr, 276 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 277 srcData = Seq( 278 Seq(IntData()), 279 ), 280 piped = true, 281 writeIntRf = true, 282 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 283 flushPipe = true, 284 ) 285 286 val AluCfg: FuConfig = FuConfig ( 287 name = "alu", 288 fuType = FuType.alu, 289 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 290 srcData = Seq( 291 Seq(IntData(), IntData()), 292 ), 293 piped = true, 294 writeIntRf = true, 295 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 296 ) 297 298 val MulCfg: FuConfig = FuConfig ( 299 name = "mul", 300 fuType = FuType.mul, 301 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 302 srcData = Seq( 303 Seq(IntData(), IntData()), 304 ), 305 piped = true, 306 writeIntRf = true, 307 latency = CertainLatency(2), 308 ) 309 310 val DivCfg: FuConfig = FuConfig ( 311 name = "div", 312 fuType = FuType.div, 313 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 314 srcData = Seq( 315 Seq(IntData(), IntData()), 316 ), 317 piped = false, 318 writeIntRf = true, 319 latency = UncertainLatency(), 320 hasInputBuffer = (true, 4, true) 321 ) 322 323 val FenceCfg: FuConfig = FuConfig ( 324 name = "fence", 325 FuType.fence, 326 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 327 srcData = Seq( 328 Seq(IntData(), IntData()), 329 ), 330 piped = true, 331 latency = CertainLatency(0), 332 exceptionOut = Seq(illegalInstr), 333 flushPipe = true 334 ) 335 336 // Todo: split it to simple bitmap exu and complex bku 337 val BkuCfg: FuConfig = FuConfig ( 338 name = "bku", 339 fuType = FuType.bku, 340 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 341 srcData = Seq( 342 Seq(IntData(), IntData()), 343 ), 344 piped = true, 345 writeIntRf = true, 346 latency = CertainLatency(2), 347 ) 348 349 val VSetRvfWvfCfg: FuConfig = FuConfig( 350 name = "vsetrvfwvf", 351 fuType = FuType.vsetfwf, 352 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 353 srcData = Seq( 354 Seq(FpData(), FpData()), 355 ), 356 piped = true, 357 writeVecRf = true, 358 latency = CertainLatency(0), 359 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 360 ) 361 362 val VSetRiWvfCfg: FuConfig = FuConfig( 363 name = "vsetriwvf", 364 fuType = FuType.vsetiwf, 365 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 366 srcData = Seq( 367 Seq(IntData(), IntData()), 368 ), 369 piped = true, 370 writeVecRf = true, 371 latency = CertainLatency(0), 372 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 373 ) 374 375 val VSetRiWiCfg: FuConfig = FuConfig( 376 name = "vsetriwi", 377 fuType = FuType.vsetiwi, 378 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 379 srcData = Seq( 380 Seq(IntData(), IntData()), 381 ), 382 piped = true, 383 writeIntRf = true, 384 latency = CertainLatency(0), 385 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 386 ) 387 388 val FmacCfg: FuConfig = FuConfig ( 389 name = "fmac", 390 fuType = FuType.fmac, 391 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 392 srcData = Seq( 393 Seq(FpData(), FpData()), 394 Seq(FpData(), FpData(), FpData()), 395 ), 396 piped = false, 397 writeFpRf = true, 398 writeFflags = true, 399 latency = UncertainLatency(), 400 needSrcFrm = true, 401 ) 402 403 val F2iCfg: FuConfig = FuConfig ( 404 name = "f2i", 405 fuType = FuType.fmisc, 406 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 407 srcData = Seq( 408 Seq(FpData(), FpData()), 409 Seq(FpData()), 410 ), 411 piped = true, 412 writeIntRf = true, 413 writeFflags = true, 414 latency = CertainLatency(2), 415 needSrcFrm = true, 416 ) 417 418 val F2fCfg: FuConfig = FuConfig ( 419 name = "f2f", 420 fuType = FuType.fmisc, 421 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 422 srcData = Seq( 423 Seq(FpData(), FpData()), 424 Seq(FpData()), 425 ), 426 piped = true, 427 writeFpRf = true, 428 writeFflags = true, 429 latency = CertainLatency(2), 430 needSrcFrm = true, 431 ) 432 433 val FDivSqrtCfg: FuConfig = FuConfig ( 434 name = "fDivSqrt", 435 fuType = FuType.fDivSqrt, 436 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 437 srcData = Seq( 438 Seq(FpData(), FpData()), 439 ), 440 piped = false, 441 writeFpRf = true, 442 writeFflags = true, 443 latency = UncertainLatency(), 444 hasInputBuffer = (true, 8, true), 445 needSrcFrm = true, 446 ) 447 448 val LduCfg: FuConfig = FuConfig ( 449 name = "ldu", 450 fuType = FuType.ldu, 451 fuGen = null, // Todo 452 srcData = Seq( 453 Seq(IntData()), 454 ), 455 piped = false, // Todo: check it 456 writeIntRf = true, 457 writeFpRf = true, 458 latency = UncertainLatency(3), 459 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 460 flushPipe = true, 461 replayInst = true, 462 hasLoadError = true, 463 trigger = true, 464 immType = Set(SelImm.IMM_I), 465 ) 466 467 val StaCfg: FuConfig = FuConfig ( 468 name = "sta", 469 fuType = FuType.stu, 470 fuGen = null, // Todo 471 srcData = Seq( 472 Seq(IntData()), 473 ), 474 piped = false, 475 latency = UncertainLatency(), 476 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 477 trigger = true, 478 immType = Set(SelImm.IMM_S), 479 ) 480 481 val StdCfg: FuConfig = FuConfig ( 482 name = "std", 483 fuType = FuType.stu, 484 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 485 srcData = Seq( 486 Seq(IntData()), 487 Seq(FpData()), 488 ), 489 piped = true, 490 latency = CertainLatency(0) 491 ) 492 493 val HyldaCfg = FuConfig ( 494 name = "hylda", 495 fuType = FuType.ldu, 496 fuGen = null, // Todo 497 srcData = Seq( 498 Seq(IntData()), 499 ), 500 piped = false, // Todo: check it 501 writeIntRf = true, 502 writeFpRf = true, 503 latency = UncertainLatency(3), 504 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 505 flushPipe = true, 506 replayInst = true, 507 hasLoadError = true, 508 immType = Set(SelImm.IMM_I), 509 ) 510 511 val HystaCfg = FuConfig ( 512 name = "hysta", 513 fuType = FuType.stu, 514 fuGen = null, // Todo 515 srcData = Seq( 516 Seq(IntData()), 517 ), 518 piped = false, 519 latency = UncertainLatency(), 520 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 521 immType = Set(SelImm.IMM_S), 522 ) 523 524 val FakeHystaCfg = FuConfig ( 525 name = "hysta", 526 fuType = FuType.stu, 527 fuGen = null, // Todo 528 srcData = Seq(), 529 piped = false, 530 latency = UncertainLatency(), 531 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 532 immType = Set(), 533 ) 534 535 val MouCfg: FuConfig = FuConfig ( 536 name = "mou", 537 fuType = FuType.mou, 538 fuGen = null, // Todo 539 srcData = Seq( 540 Seq(IntData()), 541 ), 542 piped = false, // Todo: check it 543 writeFakeIntRf = true, 544 latency = UncertainLatency(), 545 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 546 trigger = true, 547 ) 548 549 val MoudCfg: FuConfig = FuConfig ( 550 name = "moud", 551 fuType = FuType.mou, 552 fuGen = null, // Todo 553 srcData = Seq( 554 Seq(IntData()), 555 ), 556 piped = true, 557 latency = CertainLatency(0), 558 ) 559 560 val VialuCfg = FuConfig ( 561 name = "vialuFix", 562 fuType = FuType.vialuF, 563 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 564 srcData = Seq( 565 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 566 ), 567 piped = true, 568 writeVecRf = true, 569 writeVxsat = true, 570 needSrcVxrm = true, 571 latency = CertainLatency(1), 572 vconfigWakeUp = true, 573 maskWakeUp = true, 574 dataBits = 128, 575 exceptionOut = Seq(illegalInstr), 576 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 577 ) 578 579 val VimacCfg = FuConfig ( 580 name = "vimac", 581 fuType = FuType.vimac, 582 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 583 srcData = Seq( 584 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 585 ), 586 piped = true, 587 writeVecRf = true, 588 writeVxsat = true, 589 needSrcVxrm = true, 590 latency = CertainLatency(2), 591 vconfigWakeUp = true, 592 maskWakeUp = true, 593 dataBits = 128, 594 exceptionOut = Seq(illegalInstr), 595 ) 596 597 val VidivCfg = FuConfig ( 598 name = "vidiv", 599 fuType = FuType.vidiv, 600 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 601 srcData = Seq( 602 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 603 ), 604 piped = false, 605 writeVecRf = true, 606 latency = UncertainLatency(), 607 vconfigWakeUp = true, 608 maskWakeUp = true, 609 dataBits = 128, 610 exceptionOut = Seq(illegalInstr), 611 ) 612 613 val VppuCfg = FuConfig ( 614 name = "vppu", 615 fuType = FuType.vppu, 616 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 617 srcData = Seq( 618 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 619 ), 620 piped = true, 621 writeVecRf = true, 622 latency = CertainLatency(1), 623 vconfigWakeUp = true, 624 maskWakeUp = true, 625 dataBits = 128, 626 exceptionOut = Seq(illegalInstr), 627 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 628 ) 629 630 val VipuCfg: FuConfig = FuConfig ( 631 name = "vipu", 632 fuType = FuType.vipu, 633 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 634 srcData = Seq( 635 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 636 ), 637 piped = true, 638 writeIntRf = true, 639 writeVecRf = true, 640 latency = CertainLatency(1), 641 vconfigWakeUp = true, 642 maskWakeUp = true, 643 dataBits = 128, 644 exceptionOut = Seq(illegalInstr), 645 ) 646 647 val VfaluCfg = FuConfig ( 648 name = "vfalu", 649 fuType = FuType.vfalu, 650 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 651 srcData = Seq( 652 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 653 ), 654 piped = true, 655 writeVecRf = true, 656 writeFpRf = true, 657 writeIntRf = true, 658 writeFflags = true, 659 latency = CertainLatency(1), 660 vconfigWakeUp = true, 661 maskWakeUp = true, 662 dataBits = 128, 663 exceptionOut = Seq(illegalInstr), 664 ) 665 666 val VfmaCfg = FuConfig ( 667 name = "vfma", 668 fuType = FuType.vfma, 669 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 670 srcData = Seq( 671 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 672 ), 673 piped = true, 674 writeVecRf = true, 675 writeFpRf = true, 676 writeFflags = true, 677 latency = CertainLatency(3), 678 vconfigWakeUp = true, 679 maskWakeUp = true, 680 dataBits = 128, 681 exceptionOut = Seq(illegalInstr), 682 ) 683 684 val VfdivCfg = FuConfig( 685 name = "vfdiv", 686 fuType = FuType.vfdiv, 687 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 688 srcData = Seq( 689 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 690 ), 691 piped = false, 692 writeVecRf = true, 693 writeFpRf = true, 694 writeFflags = true, 695 latency = UncertainLatency(), 696 vconfigWakeUp = true, 697 maskWakeUp = true, 698 dataBits = 128, 699 exceptionOut = Seq(illegalInstr), 700 ) 701 702 val VfcvtCfg = FuConfig( 703 name = "vfcvt", 704 fuType = FuType.vfcvt, 705 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 706 srcData = Seq( 707 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 708 ), 709 piped = true, 710 writeVecRf = true, 711 writeFpRf = false, 712 writeFflags = true, 713 latency = CertainLatency(2), 714 vconfigWakeUp = true, 715 maskWakeUp = true, 716 dataBits = 128, 717 exceptionOut = Seq(illegalInstr), 718 ) 719 720 721 val VlduCfg: FuConfig = FuConfig ( 722 name = "vldu", 723 fuType = FuType.vldu, 724 fuGen = null, 725 srcData = Seq( 726 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 727 ), 728 piped = false, // Todo: check it 729 writeVecRf = true, 730 latency = UncertainLatency(), 731 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 732 flushPipe = true, 733 replayInst = true, 734 hasLoadError = true, 735 vconfigWakeUp = true, 736 maskWakeUp = true, 737 dataBits = 128, 738 ) 739 740 val VstuCfg: FuConfig = FuConfig ( 741 name = "vstu", 742 fuType = FuType.vstu, 743 fuGen = null, 744 srcData = Seq( 745 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 746 ), 747 piped = false, 748 writeVecRf = false, 749 latency = UncertainLatency(), 750 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 751 flushPipe = true, 752 replayInst = true, 753 hasLoadError = true, 754 vconfigWakeUp = true, 755 maskWakeUp = true, 756 dataBits = 128, 757 ) 758 759 def allConfigs = Seq( 760 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 761 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 762 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 763 ) 764 765 def VecArithFuConfigs = Seq( 766 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 767 ) 768} 769 770