1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).max 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).max 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).max 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).max 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).max 86 def numSrc : Int = srcData.map(_.length).max 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).max 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 /** 167 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 168 * @param data [[DataConfig]] 169 * @param tips tips if get failed 170 * @return the index of special src data 171 */ 172 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 173 val srcIdxVec = srcData.map(x => x.indexOf(data)) 174 val idx0 = srcIdxVec.head 175 for (idx <- srcIdxVec) { 176 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 177 } 178 idx0 179 } 180 181 override def toString: String = { 182 var str = s"${this.name}: " 183 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 184 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 185 str += s"latency($latency)" 186 str 187 } 188} 189 190object FuConfig { 191 val JmpCfg: FuConfig = FuConfig ( 192 name = "jmp", 193 fuType = FuType.jmp, 194 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 195 srcData = Seq( 196 Seq(IntData()), // jal 197 ), 198 piped = true, 199 writeIntRf = true, 200 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 201 ) 202 203 val BrhCfg: FuConfig = FuConfig ( 204 name = "brh", 205 fuType = FuType.brh, 206 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 207 srcData = Seq( 208 Seq(IntData(), IntData()), 209 ), 210 piped = true, 211 immType = Set(SelImm.IMM_SB), 212 ) 213 214 val I2fCfg: FuConfig = FuConfig ( 215 name = "i2f", 216 FuType.i2f, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 218 srcData = Seq( 219 Seq(IntData()), 220 ), 221 piped = true, 222 writeFpRf = true, 223 writeFflags = true, 224 latency = CertainLatency(2), 225 needSrcFrm = true, 226 ) 227 228 val I2vCfg: FuConfig = FuConfig ( 229 name = "i2v", 230 FuType.i2v, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 232 srcData = Seq( 233 Seq(IntData(), IntData()), 234 ), 235 piped = true, 236 writeVecRf = true, 237 latency = CertainLatency(0), 238 dataBits = 128, 239 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 240 ) 241 242 val CsrCfg: FuConfig = FuConfig ( 243 name = "csr", 244 fuType = FuType.csr, 245 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 246 srcData = Seq( 247 Seq(IntData()), 248 ), 249 piped = true, 250 writeIntRf = true, 251 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 252 flushPipe = true, 253 ) 254 255 val AluCfg: FuConfig = FuConfig ( 256 name = "alu", 257 fuType = FuType.alu, 258 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 259 srcData = Seq( 260 Seq(IntData(), IntData()), 261 ), 262 piped = true, 263 writeIntRf = true, 264 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 265 ) 266 267 val MulCfg: FuConfig = FuConfig ( 268 name = "mul", 269 fuType = FuType.mul, 270 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 271 srcData = Seq( 272 Seq(IntData(), IntData()), 273 ), 274 piped = true, 275 writeIntRf = true, 276 latency = CertainLatency(2), 277 ) 278 279 val DivCfg: FuConfig = FuConfig ( 280 name = "div", 281 fuType = FuType.div, 282 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 283 srcData = Seq( 284 Seq(IntData(), IntData()), 285 ), 286 piped = false, 287 writeIntRf = true, 288 latency = UncertainLatency(), 289 hasInputBuffer = (true, 4, true) 290 ) 291 292 val FenceCfg: FuConfig = FuConfig ( 293 name = "fence", 294 FuType.fence, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 296 srcData = Seq( 297 Seq(IntData(), IntData()), 298 ), 299 piped = true, 300 latency = CertainLatency(0), 301 exceptionOut = Seq(illegalInstr), 302 flushPipe = true 303 ) 304 305 // Todo: split it to simple bitmap exu and complex bku 306 val BkuCfg: FuConfig = FuConfig ( 307 name = "bku", 308 fuType = FuType.bku, 309 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 310 srcData = Seq( 311 Seq(IntData(), IntData()), 312 ), 313 piped = true, 314 writeIntRf = true, 315 latency = CertainLatency(2), 316 ) 317 318 val VSetRvfWvfCfg: FuConfig = FuConfig( 319 name = "vsetrvfwvf", 320 fuType = FuType.vsetiwf, 321 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 322 srcData = Seq( 323 Seq(FpData(), FpData()), 324 ), 325 piped = true, 326 writeVecRf = true, 327 latency = CertainLatency(0), 328 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 329 ) 330 331 val VSetRiWvfCfg: FuConfig = FuConfig( 332 name = "vsetriwvf", 333 fuType = FuType.vsetiwf, 334 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 335 srcData = Seq( 336 Seq(IntData(), IntData()), 337 ), 338 piped = true, 339 writeVecRf = true, 340 latency = CertainLatency(0), 341 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 342 ) 343 344 val VSetRiWiCfg: FuConfig = FuConfig( 345 name = "vsetriwi", 346 fuType = FuType.vsetiwi, 347 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 348 srcData = Seq( 349 Seq(IntData(), IntData()), 350 ), 351 piped = true, 352 writeIntRf = true, 353 latency = CertainLatency(0), 354 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 355 ) 356 357 val FmacCfg: FuConfig = FuConfig ( 358 name = "fmac", 359 fuType = FuType.fmac, 360 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 361 srcData = Seq( 362 Seq(FpData(), FpData()), 363 Seq(FpData(), FpData(), FpData()), 364 ), 365 piped = false, 366 writeFpRf = true, 367 writeFflags = true, 368 latency = UncertainLatency(), 369 needSrcFrm = true, 370 ) 371 372 val F2iCfg: FuConfig = FuConfig ( 373 name = "f2i", 374 fuType = FuType.fmisc, 375 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 376 srcData = Seq( 377 Seq(FpData(), FpData()), 378 Seq(FpData()), 379 ), 380 piped = true, 381 writeIntRf = true, 382 writeFflags = true, 383 latency = CertainLatency(2), 384 needSrcFrm = true, 385 ) 386 387 val F2fCfg: FuConfig = FuConfig ( 388 name = "f2f", 389 fuType = FuType.fmisc, 390 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 391 srcData = Seq( 392 Seq(FpData(), FpData()), 393 Seq(FpData()), 394 ), 395 piped = true, 396 writeFpRf = true, 397 writeFflags = true, 398 latency = CertainLatency(2), 399 needSrcFrm = true, 400 ) 401 402 val FDivSqrtCfg: FuConfig = FuConfig ( 403 name = "fDivSqrt", 404 fuType = FuType.fDivSqrt, 405 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 406 srcData = Seq( 407 Seq(FpData(), FpData()), 408 ), 409 piped = false, 410 writeFpRf = true, 411 writeFflags = true, 412 latency = UncertainLatency(), 413 hasInputBuffer = (true, 8, true), 414 needSrcFrm = true, 415 ) 416 417 val LduCfg: FuConfig = FuConfig ( 418 name = "ldu", 419 fuType = FuType.ldu, 420 fuGen = null, // Todo 421 srcData = Seq( 422 Seq(IntData()), 423 ), 424 piped = false, // Todo: check it 425 writeIntRf = true, 426 writeFpRf = true, 427 latency = UncertainLatency(3), 428 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 429 flushPipe = true, 430 replayInst = true, 431 hasLoadError = true, 432 immType = Set(SelImm.IMM_I), 433 ) 434 435 val StaCfg: FuConfig = FuConfig ( 436 name = "sta", 437 fuType = FuType.stu, 438 fuGen = null, // Todo 439 srcData = Seq( 440 Seq(IntData()), 441 ), 442 piped = false, 443 latency = UncertainLatency(), 444 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 445 immType = Set(SelImm.IMM_S), 446 ) 447 448 val StdCfg: FuConfig = FuConfig ( 449 name = "std", 450 fuType = FuType.stu, 451 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 452 srcData = Seq( 453 Seq(IntData()), 454 Seq(FpData()), 455 ), 456 piped = true, 457 latency = CertainLatency(0) 458 ) 459 460 val MouCfg: FuConfig = FuConfig ( 461 name = "mou", 462 fuType = FuType.mou, 463 fuGen = null, // Todo 464 srcData = Seq( 465 Seq(IntData()), 466 ), 467 piped = false, // Todo: check it 468 writeIntRf = true, 469 latency = UncertainLatency(), 470 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct 471 ) 472 473 val MoudCfg: FuConfig = FuConfig ( 474 name = "moud", 475 fuType = FuType.mou, 476 fuGen = null, // Todo 477 srcData = Seq( 478 Seq(IntData()), 479 ), 480 piped = true, 481 latency = CertainLatency(0), 482 ) 483 484 val VialuCfg = FuConfig ( 485 name = "vialuFix", 486 fuType = FuType.vialuF, 487 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 488 srcData = Seq( 489 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 490 ), 491 piped = true, 492 writeVecRf = true, 493 writeVxsat = true, 494 latency = CertainLatency(1), 495 vconfigWakeUp = true, 496 maskWakeUp = true, 497 dataBits = 128, 498 exceptionOut = Seq(illegalInstr), 499 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 500 ) 501 502 val VimacCfg = FuConfig ( 503 name = "vimac", 504 fuType = FuType.vimac, 505 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 506 srcData = Seq( 507 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 508 ), 509 piped = true, 510 writeVecRf = true, 511 writeVxsat = true, 512 latency = CertainLatency(2), 513 vconfigWakeUp = true, 514 maskWakeUp = true, 515 dataBits = 128, 516 exceptionOut = Seq(illegalInstr), 517 ) 518 519 val VppuCfg = FuConfig ( 520 name = "vppu", 521 fuType = FuType.vppu, 522 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 523 srcData = Seq( 524 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 525 ), 526 piped = true, 527 writeVecRf = true, 528 writeVxsat = true, 529 latency = CertainLatency(1), 530 vconfigWakeUp = true, 531 maskWakeUp = true, 532 dataBits = 128, 533 exceptionOut = Seq(illegalInstr), 534 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 535 ) 536 537 val VipuCfg: FuConfig = FuConfig ( 538 name = "vipu", 539 fuType = FuType.vipu, 540 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 541 srcData = Seq( 542 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 543 ), 544 piped = true, 545 writeVecRf = true, 546 latency = CertainLatency(1), 547 vconfigWakeUp = true, 548 maskWakeUp = true, 549 dataBits = 128, 550 exceptionOut = Seq(illegalInstr), 551 ) 552 553 val VfaluCfg = FuConfig ( 554 name = "vfalu", 555 fuType = FuType.vfalu, 556 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 557 srcData = Seq( 558 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 559 ), 560 piped = true, 561 writeVecRf = true, 562 writeFpRf = true, 563 writeIntRf = true, 564 writeFflags = true, 565 latency = CertainLatency(1), 566 vconfigWakeUp = true, 567 maskWakeUp = true, 568 dataBits = 128, 569 exceptionOut = Seq(illegalInstr), 570 ) 571 572 val VfmaCfg = FuConfig ( 573 name = "vfma", 574 fuType = FuType.vfma, 575 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 576 srcData = Seq( 577 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 578 ), 579 piped = true, 580 writeVecRf = true, 581 writeFpRf = true, 582 writeFflags = true, 583 latency = CertainLatency(3), 584 vconfigWakeUp = true, 585 maskWakeUp = true, 586 dataBits = 128, 587 exceptionOut = Seq(illegalInstr), 588 ) 589 590 val VfdivCfg = FuConfig( 591 name = "vfdiv", 592 fuType = FuType.vfdiv, 593 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 594 srcData = Seq( 595 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 596 ), 597 piped = false, 598 writeVecRf = true, 599 writeFpRf = true, 600 writeFflags = true, 601 latency = UncertainLatency(), 602 vconfigWakeUp = true, 603 maskWakeUp = true, 604 dataBits = 128, 605 exceptionOut = Seq(illegalInstr), 606 ) 607 608 val VfcvtCfg = FuConfig( 609 name = "vfcvt", 610 fuType = FuType.vfcvt, 611 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 612 srcData = Seq( 613 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 614 ), 615 piped = true, 616 writeVecRf = true, 617 writeFpRf = false, 618 writeFflags = true, 619 latency = CertainLatency(2), 620 vconfigWakeUp = true, 621 maskWakeUp = true, 622 dataBits = 128, 623 exceptionOut = Seq(illegalInstr), 624 ) 625 626 627 val VlduCfg: FuConfig = FuConfig ( 628 name = "vldu", 629 fuType = FuType.vldu, 630 fuGen = null, 631 srcData = Seq( 632 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 633 ), 634 piped = false, // Todo: check it 635 writeVecRf = true, 636 latency = UncertainLatency(), 637 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 638 flushPipe = true, 639 replayInst = true, 640 hasLoadError = true, 641 vconfigWakeUp = true, 642 maskWakeUp = true, 643 dataBits = 128, 644 ) 645 //TODO 646 // def VstuCfg = FuConfig () 647 648 def allConfigs = Seq( 649 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 650 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, 651 VfaluCfg, VfmaCfg 652 ) 653 654 def VecArithFuConfigs = Seq( 655 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 656 ) 657} 658 659