1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect is in its exception bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf 182 183 def isSta: Boolean = name.contains("sta") 184 185 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 186 fuType == FuType.div || fuType == FuType.fDivSqrt || 187 fuType == FuType.vfdiv || fuType == FuType.vidiv 188 189 /** 190 * Get index of special src data, like [[VlData]], [[V0Data]] 191 * 192 * @param data [[DataConfig]] 193 * @param tips tips if get failed 194 * @return the index of special src data 195 */ 196 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 197 val srcIdxVec = srcData.map(x => x.indexOf(data)) 198 val idx0 = srcIdxVec.head 199 for (idx <- srcIdxVec) { 200 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 201 } 202 idx0 203 } 204 205 override def toString: String = { 206 var str = s"${this.name}: " 207 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 208 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 209 str += s"latency($latency)" 210 str += s"src($srcData)" 211 str 212 } 213} 214 215object FuConfig { 216 val JmpCfg: FuConfig = FuConfig ( 217 name = "jmp", 218 fuType = FuType.jmp, 219 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 220 srcData = Seq( 221 Seq(IntData()), // jal 222 ), 223 piped = true, 224 writeIntRf = true, 225 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 226 ) 227 228 val BrhCfg: FuConfig = FuConfig ( 229 name = "brh", 230 fuType = FuType.brh, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 232 srcData = Seq( 233 Seq(IntData(), IntData()), 234 ), 235 piped = true, 236 immType = Set(SelImm.IMM_SB), 237 ) 238 239 val I2fCfg: FuConfig = FuConfig ( 240 name = "i2f", 241 FuType.i2f, 242 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 243 srcData = Seq( 244 Seq(IntData()), 245 ), 246 piped = true, 247 writeFpRf = true, 248 writeFflags = true, 249 latency = CertainLatency(2), 250 needSrcFrm = true, 251 ) 252 253 val I2vCfg: FuConfig = FuConfig ( 254 name = "i2v", 255 FuType.i2v, 256 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 257 srcData = Seq( 258 Seq(IntData(), IntData()), 259 ), 260 piped = true, 261 writeFpRf = true, 262 writeVecRf = true, 263 writeV0Rf = true, 264 latency = CertainLatency(0), 265 destDataBits = 128, 266 srcDataBits = Some(64), 267 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 268 ) 269 270 val F2vCfg: FuConfig = FuConfig ( 271 name = "f2v", 272 FuType.f2v, 273 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 274 srcData = Seq( 275 Seq(FpData(), FpData()), 276 Seq(FpData()), 277 ), 278 piped = true, 279 writeVecRf = true, 280 writeV0Rf = true, 281 latency = CertainLatency(0), 282 destDataBits = 128, 283 srcDataBits = Some(64), 284 ) 285 286 val CsrCfg: FuConfig = FuConfig ( 287 name = "csr", 288 fuType = FuType.csr, 289 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 290 srcData = Seq( 291 Seq(IntData()), 292 ), 293 piped = true, 294 writeIntRf = true, 295 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 296 flushPipe = true, 297 ) 298 299 val AluCfg: FuConfig = FuConfig ( 300 name = "alu", 301 fuType = FuType.alu, 302 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 303 srcData = Seq( 304 Seq(IntData(), IntData()), 305 ), 306 piped = true, 307 writeIntRf = true, 308 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 309 ) 310 311 val MulCfg: FuConfig = FuConfig ( 312 name = "mul", 313 fuType = FuType.mul, 314 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 315 srcData = Seq( 316 Seq(IntData(), IntData()), 317 ), 318 piped = true, 319 writeIntRf = true, 320 latency = CertainLatency(2), 321 ) 322 323 val DivCfg: FuConfig = FuConfig ( 324 name = "div", 325 fuType = FuType.div, 326 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 327 srcData = Seq( 328 Seq(IntData(), IntData()), 329 ), 330 piped = false, 331 writeIntRf = true, 332 latency = UncertainLatency(), 333 hasInputBuffer = (true, 4, true) 334 ) 335 336 val FenceCfg: FuConfig = FuConfig ( 337 name = "fence", 338 FuType.fence, 339 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 340 srcData = Seq( 341 Seq(IntData(), IntData()), 342 ), 343 piped = true, 344 latency = CertainLatency(0), 345 exceptionOut = Seq(illegalInstr, virtualInstr), 346 flushPipe = true 347 ) 348 349 // Todo: split it to simple bitmap exu and complex bku 350 val BkuCfg: FuConfig = FuConfig ( 351 name = "bku", 352 fuType = FuType.bku, 353 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 354 srcData = Seq( 355 Seq(IntData(), IntData()), 356 ), 357 piped = true, 358 writeIntRf = true, 359 latency = CertainLatency(2), 360 ) 361 362 val VSetRvfWvfCfg: FuConfig = FuConfig( 363 name = "vsetrvfwvf", 364 fuType = FuType.vsetfwf, 365 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 366 srcData = Seq( 367 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 368 ), 369 piped = true, 370 writeVlRf = true, 371 writeVType = true, 372 writeIntRf = true, 373 latency = CertainLatency(0), 374 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 375 ) 376 377 val VSetRiWvfCfg: FuConfig = FuConfig( 378 name = "vsetriwvf", 379 fuType = FuType.vsetiwf, 380 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 381 srcData = Seq( 382 Seq(IntData(), IntData()), 383 ), 384 piped = true, 385 writeVlRf = true, 386 writeVType = true, 387 latency = CertainLatency(0), 388 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 389 ) 390 391 val VSetRiWiCfg: FuConfig = FuConfig( 392 name = "vsetriwi", 393 fuType = FuType.vsetiwi, 394 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 395 srcData = Seq( 396 Seq(IntData(), IntData()), 397 ), 398 piped = true, 399 writeIntRf = true, 400 latency = CertainLatency(0), 401 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 402 ) 403 404 val LduCfg: FuConfig = FuConfig ( 405 name = "ldu", 406 fuType = FuType.ldu, 407 fuGen = null, // Todo 408 srcData = Seq( 409 Seq(IntData()), 410 ), 411 piped = false, // Todo: check it 412 writeIntRf = true, 413 writeFpRf = true, 414 latency = UncertainLatency(3), 415 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 416 flushPipe = true, 417 replayInst = true, 418 hasLoadError = true, 419 trigger = true, 420 immType = Set(SelImm.IMM_I), 421 ) 422 423 val StaCfg: FuConfig = FuConfig ( 424 name = "sta", 425 fuType = FuType.stu, 426 fuGen = null, // Todo 427 srcData = Seq( 428 Seq(IntData()), 429 ), 430 piped = false, 431 latency = UncertainLatency(), 432 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 433 trigger = true, 434 immType = Set(SelImm.IMM_S), 435 ) 436 437 val StdCfg: FuConfig = FuConfig ( 438 name = "std", 439 fuType = FuType.stu, 440 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 441 srcData = Seq( 442 Seq(IntData()), 443 Seq(FpData()), 444 ), 445 piped = true, 446 latency = CertainLatency(0) 447 ) 448 449 val HyldaCfg = FuConfig ( 450 name = "hylda", 451 fuType = FuType.ldu, 452 fuGen = null, // Todo 453 srcData = Seq( 454 Seq(IntData()), 455 ), 456 piped = false, // Todo: check it 457 writeIntRf = true, 458 writeFpRf = true, 459 latency = UncertainLatency(3), 460 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 461 flushPipe = true, 462 replayInst = true, 463 hasLoadError = true, 464 immType = Set(SelImm.IMM_I), 465 ) 466 467 val HystaCfg = FuConfig ( 468 name = "hysta", 469 fuType = FuType.stu, 470 fuGen = null, // Todo 471 srcData = Seq( 472 Seq(IntData()), 473 ), 474 piped = false, 475 latency = UncertainLatency(), 476 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 477 immType = Set(SelImm.IMM_S), 478 ) 479 480 val FakeHystaCfg = FuConfig ( 481 name = "hysta", 482 fuType = FuType.stu, 483 fuGen = null, // Todo 484 srcData = Seq(), 485 piped = false, 486 latency = UncertainLatency(), 487 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 488 immType = Set(), 489 ) 490 491 val MouCfg: FuConfig = FuConfig ( 492 name = "mou", 493 fuType = FuType.mou, 494 fuGen = null, // Todo 495 srcData = Seq( 496 Seq(IntData()), 497 ), 498 piped = false, // Todo: check it 499 writeFakeIntRf = true, 500 latency = UncertainLatency(), 501 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 502 trigger = true, 503 ) 504 505 val MoudCfg: FuConfig = FuConfig ( 506 name = "moud", 507 fuType = FuType.mou, 508 fuGen = null, // Todo 509 srcData = Seq( 510 Seq(IntData()), 511 ), 512 piped = true, 513 latency = CertainLatency(0), 514 ) 515 516 val VialuCfg = FuConfig ( 517 name = "vialuFix", 518 fuType = FuType.vialuF, 519 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 520 srcData = Seq( 521 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 522 ), 523 piped = true, 524 writeVecRf = true, 525 writeV0Rf = true, 526 writeVxsat = true, 527 needSrcVxrm = true, 528 latency = CertainLatency(1), 529 vconfigWakeUp = true, 530 maskWakeUp = true, 531 destDataBits = 128, 532 exceptionOut = Seq(illegalInstr), 533 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 534 ) 535 536 val VimacCfg = FuConfig ( 537 name = "vimac", 538 fuType = FuType.vimac, 539 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 540 srcData = Seq( 541 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 542 ), 543 piped = true, 544 writeVecRf = true, 545 writeV0Rf = true, 546 writeVxsat = true, 547 needSrcVxrm = true, 548 latency = CertainLatency(2), 549 vconfigWakeUp = true, 550 maskWakeUp = true, 551 destDataBits = 128, 552 exceptionOut = Seq(illegalInstr), 553 ) 554 555 val VidivCfg = FuConfig ( 556 name = "vidiv", 557 fuType = FuType.vidiv, 558 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 559 srcData = Seq( 560 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 561 ), 562 piped = false, 563 writeVecRf = true, 564 writeV0Rf = true, 565 latency = UncertainLatency(), 566 vconfigWakeUp = true, 567 maskWakeUp = true, 568 destDataBits = 128, 569 exceptionOut = Seq(illegalInstr), 570 ) 571 572 val VppuCfg = FuConfig ( 573 name = "vppu", 574 fuType = FuType.vppu, 575 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 576 srcData = Seq( 577 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 578 ), 579 piped = true, 580 writeVecRf = true, 581 writeV0Rf = true, 582 latency = CertainLatency(2), 583 vconfigWakeUp = true, 584 maskWakeUp = true, 585 destDataBits = 128, 586 exceptionOut = Seq(illegalInstr), 587 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 588 ) 589 590 val VipuCfg: FuConfig = FuConfig ( 591 name = "vipu", 592 fuType = FuType.vipu, 593 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 594 srcData = Seq( 595 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 596 ), 597 piped = true, 598 writeIntRf = true, 599 writeVecRf = true, 600 writeV0Rf = true, 601 latency = CertainLatency(2), 602 vconfigWakeUp = true, 603 maskWakeUp = true, 604 destDataBits = 128, 605 exceptionOut = Seq(illegalInstr), 606 ) 607 608 val VfaluCfg = FuConfig ( 609 name = "vfalu", 610 fuType = FuType.vfalu, 611 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 612 srcData = Seq( 613 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 614 ), 615 piped = true, 616 writeVecRf = true, 617 writeV0Rf = true, 618 writeFpRf = true, 619 writeFflags = true, 620 latency = CertainLatency(1), 621 vconfigWakeUp = true, 622 maskWakeUp = true, 623 destDataBits = 128, 624 exceptionOut = Seq(illegalInstr), 625 needSrcFrm = true, 626 ) 627 628 val VfmaCfg = FuConfig ( 629 name = "vfma", 630 fuType = FuType.vfma, 631 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 632 srcData = Seq( 633 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 634 ), 635 piped = true, 636 writeVecRf = true, 637 writeV0Rf = true, 638 writeFflags = true, 639 latency = CertainLatency(3), 640 vconfigWakeUp = true, 641 maskWakeUp = true, 642 destDataBits = 128, 643 exceptionOut = Seq(illegalInstr), 644 needSrcFrm = true, 645 ) 646 647 val VfdivCfg = FuConfig( 648 name = "vfdiv", 649 fuType = FuType.vfdiv, 650 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 651 srcData = Seq( 652 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 653 ), 654 piped = false, 655 writeVecRf = true, 656 writeV0Rf = true, 657 writeFflags = true, 658 latency = UncertainLatency(), 659 vconfigWakeUp = true, 660 maskWakeUp = true, 661 destDataBits = 128, 662 exceptionOut = Seq(illegalInstr), 663 needSrcFrm = true, 664 ) 665 666 val VfcvtCfg = FuConfig( 667 name = "vfcvt", 668 fuType = FuType.vfcvt, 669 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 670 srcData = Seq( 671 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 672 ), 673 piped = true, 674 writeVecRf = true, 675 writeV0Rf = true, 676 writeFflags = true, 677 latency = CertainLatency(2), 678 vconfigWakeUp = true, 679 maskWakeUp = true, 680 destDataBits = 128, 681 exceptionOut = Seq(illegalInstr), 682 needSrcFrm = true, 683 ) 684 685 val FaluCfg = FuConfig( 686 name = "falu", 687 fuType = FuType.falu, 688 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 689 srcData = Seq( 690 Seq(FpData(), FpData()), 691 ), 692 piped = true, 693 writeFpRf = true, 694 writeIntRf = true, 695 writeFflags = true, 696 latency = CertainLatency(1), 697 destDataBits = 64, 698 needSrcFrm = true, 699 ) 700 701 val FmacCfg = FuConfig( 702 name = "fmac", 703 fuType = FuType.fmac, 704 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 705 srcData = Seq( 706 Seq(FpData(), FpData(), FpData()), 707 ), 708 piped = true, 709 writeFpRf = true, 710 writeFflags = true, 711 latency = CertainLatency(3), 712 destDataBits = 64, 713 needSrcFrm = true, 714 ) 715 716 val FdivCfg = FuConfig( 717 name = "fdiv", 718 fuType = FuType.fDivSqrt, 719 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 720 srcData = Seq( 721 Seq(FpData(), FpData()), 722 ), 723 piped = false, 724 writeFpRf = true, 725 writeFflags = true, 726 latency = UncertainLatency(), 727 destDataBits = 64, 728 needSrcFrm = true, 729 ) 730 731 val FcvtCfg = FuConfig( 732 name = "fcvt", 733 fuType = FuType.fcvt, 734 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 735 srcData = Seq( 736 Seq(FpData()), 737 ), 738 piped = true, 739 writeFpRf = true, 740 writeIntRf = true, 741 writeFflags = true, 742 latency = CertainLatency(2), 743 destDataBits = 64, 744 needSrcFrm = true, 745 ) 746 747 val VlduCfg: FuConfig = FuConfig ( 748 name = "vldu", 749 fuType = FuType.vldu, 750 fuGen = null, 751 srcData = Seq( 752 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 753 ), 754 piped = false, // Todo: check it 755 writeVecRf = true, 756 writeV0Rf = true, 757 latency = UncertainLatency(), 758 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 759 flushPipe = true, 760 replayInst = true, 761 hasLoadError = true, 762 vconfigWakeUp = true, 763 maskWakeUp = true, 764 destDataBits = 128, 765 ) 766 767 val VstuCfg: FuConfig = FuConfig ( 768 name = "vstu", 769 fuType = FuType.vstu, 770 fuGen = null, 771 srcData = Seq( 772 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 773 ), 774 piped = false, 775 latency = UncertainLatency(), 776 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 777 flushPipe = true, 778 replayInst = true, 779 hasLoadError = true, 780 vconfigWakeUp = true, 781 maskWakeUp = true, 782 destDataBits = 128, 783 ) 784 785 val VseglduSeg: FuConfig = FuConfig ( 786 name = "vsegldu", 787 fuType = FuType.vsegldu, 788 fuGen = null, 789 srcData = Seq( 790 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 791 ), 792 piped = false, // Todo: check it 793 writeVecRf = true, 794 writeV0Rf = true, 795 latency = UncertainLatency(), 796 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 797 flushPipe = true, 798 replayInst = true, 799 hasLoadError = true, 800 vconfigWakeUp = true, 801 maskWakeUp = true, 802 destDataBits = 128, 803 ) 804 805 val VsegstuCfg: FuConfig = FuConfig( 806 name = "vsegstu", 807 fuType = FuType.vsegstu, 808 fuGen = null, 809 srcData = Seq( 810 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 811 ), 812 piped = false, 813 latency = UncertainLatency(), 814 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 815 flushPipe = true, 816 replayInst = true, 817 hasLoadError = true, 818 vconfigWakeUp = true, 819 maskWakeUp = true, 820 destDataBits = 128, 821 ) 822 823 def allConfigs = Seq( 824 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 825 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 826 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 827 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 828 ) 829 830 def VecArithFuConfigs = Seq( 831 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 832 ) 833} 834 835