1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).max 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).max 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).max 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).max 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).max 86 def numSrc : Int = srcData.map(_.length).max 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).max 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 /** 167 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 168 * @param data [[DataConfig]] 169 * @param tips tips if get failed 170 * @return the index of special src data 171 */ 172 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 173 val srcIdxVec = srcData.map(x => x.indexOf(data)) 174 val idx0 = srcIdxVec.head 175 for (idx <- srcIdxVec) { 176 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 177 } 178 idx0 179 } 180 181 override def toString: String = { 182 var str = s"${this.name}: " 183 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 184 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 185 str += s"latency($latency)" 186 str 187 } 188} 189 190object FuConfig { 191 val JmpCfg: FuConfig = FuConfig ( 192 name = "jmp", 193 fuType = FuType.jmp, 194 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 195 srcData = Seq( 196 Seq(IntData()), // jal 197 ), 198 piped = true, 199 writeIntRf = true, 200 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 201 ) 202 203 val BrhCfg: FuConfig = FuConfig ( 204 name = "brh", 205 fuType = FuType.brh, 206 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 207 srcData = Seq( 208 Seq(IntData(), IntData()), 209 ), 210 piped = true, 211 immType = Set(SelImm.IMM_SB), 212 ) 213 214 val I2fCfg: FuConfig = FuConfig ( 215 name = "i2f", 216 FuType.i2f, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 218 srcData = Seq( 219 Seq(IntData()), 220 ), 221 piped = true, 222 writeFpRf = true, 223 writeFflags = true, 224 latency = CertainLatency(2), 225 needSrcFrm = true, 226 ) 227 228 val CsrCfg: FuConfig = FuConfig ( 229 name = "csr", 230 fuType = FuType.csr, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 232 srcData = Seq( 233 Seq(IntData()), 234 ), 235 piped = true, 236 writeIntRf = true, 237 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 238 flushPipe = true, 239 ) 240 241 val AluCfg: FuConfig = FuConfig ( 242 name = "alu", 243 fuType = FuType.alu, 244 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 245 srcData = Seq( 246 Seq(IntData(), IntData()), 247 ), 248 piped = true, 249 writeIntRf = true, 250 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 251 ) 252 253 val MulCfg: FuConfig = FuConfig ( 254 name = "mul", 255 fuType = FuType.mul, 256 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 257 srcData = Seq( 258 Seq(IntData(), IntData()), 259 ), 260 piped = true, 261 writeIntRf = true, 262 latency = CertainLatency(2), 263 ) 264 265 val DivCfg: FuConfig = FuConfig ( 266 name = "div", 267 fuType = FuType.div, 268 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 269 srcData = Seq( 270 Seq(IntData(), IntData()), 271 ), 272 piped = false, 273 writeIntRf = true, 274 latency = UncertainLatency(), 275 hasInputBuffer = (true, 4, true) 276 ) 277 278 val FenceCfg: FuConfig = FuConfig ( 279 name = "fence", 280 FuType.fence, 281 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 282 srcData = Seq( 283 Seq(IntData(), IntData()), 284 ), 285 piped = true, 286 latency = CertainLatency(0), 287 exceptionOut = Seq(illegalInstr), 288 flushPipe = true 289 ) 290 291 // Todo: split it to simple bitmap exu and complex bku 292 val BkuCfg: FuConfig = FuConfig ( 293 name = "bku", 294 fuType = FuType.bku, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 296 srcData = Seq( 297 Seq(IntData(), IntData()), 298 ), 299 piped = true, 300 writeIntRf = true, 301 latency = CertainLatency(2), 302 ) 303 304 val VSetRvfWvfCfg: FuConfig = FuConfig( 305 name = "vsetrvfwvf", 306 fuType = FuType.vsetiwf, 307 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 308 srcData = Seq( 309 Seq(FpData(), FpData()), 310 ), 311 piped = true, 312 writeVecRf = true, 313 latency = CertainLatency(0), 314 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 315 ) 316 317 val VSetRiWvfCfg: FuConfig = FuConfig( 318 name = "vsetriwvf", 319 fuType = FuType.vsetiwf, 320 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 321 srcData = Seq( 322 Seq(IntData(), IntData()), 323 ), 324 piped = true, 325 writeVecRf = true, 326 latency = CertainLatency(0), 327 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 328 ) 329 330 val VSetRiWiCfg: FuConfig = FuConfig( 331 name = "vsetriwi", 332 fuType = FuType.vsetiwi, 333 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 334 srcData = Seq( 335 Seq(IntData(), IntData()), 336 ), 337 piped = true, 338 writeIntRf = true, 339 latency = CertainLatency(0), 340 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 341 ) 342 343 val FmacCfg: FuConfig = FuConfig ( 344 name = "fmac", 345 fuType = FuType.fmac, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 347 srcData = Seq( 348 Seq(FpData(), FpData()), 349 Seq(FpData(), FpData(), FpData()), 350 ), 351 piped = false, 352 writeFpRf = true, 353 writeFflags = true, 354 latency = UncertainLatency(), 355 needSrcFrm = true, 356 ) 357 358 val F2iCfg: FuConfig = FuConfig ( 359 name = "f2i", 360 fuType = FuType.fmisc, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 362 srcData = Seq( 363 Seq(FpData(), FpData()), 364 Seq(FpData()), 365 ), 366 piped = true, 367 writeIntRf = true, 368 writeFflags = true, 369 latency = CertainLatency(2), 370 needSrcFrm = true, 371 ) 372 373 val F2fCfg: FuConfig = FuConfig ( 374 name = "f2f", 375 fuType = FuType.fmisc, 376 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 377 srcData = Seq( 378 Seq(FpData(), FpData()), 379 Seq(FpData()), 380 ), 381 piped = true, 382 writeFpRf = true, 383 writeFflags = true, 384 latency = CertainLatency(2), 385 needSrcFrm = true, 386 ) 387 388 val FDivSqrtCfg: FuConfig = FuConfig ( 389 name = "fDivSqrt", 390 fuType = FuType.fDivSqrt, 391 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 392 srcData = Seq( 393 Seq(FpData(), FpData()), 394 ), 395 piped = false, 396 writeFpRf = true, 397 writeFflags = true, 398 latency = UncertainLatency(), 399 hasInputBuffer = (true, 8, true), 400 needSrcFrm = true, 401 ) 402 403 val LduCfg: FuConfig = FuConfig ( 404 name = "ldu", 405 fuType = FuType.ldu, 406 fuGen = null, // Todo 407 srcData = Seq( 408 Seq(IntData()), 409 ), 410 piped = false, // Todo: check it 411 writeIntRf = true, 412 writeFpRf = true, 413 latency = UncertainLatency(3), 414 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 415 flushPipe = true, 416 replayInst = true, 417 hasLoadError = true, 418 immType = Set(SelImm.IMM_I), 419 ) 420 421 val StaCfg: FuConfig = FuConfig ( 422 name = "sta", 423 fuType = FuType.stu, 424 fuGen = null, // Todo 425 srcData = Seq( 426 Seq(IntData()), 427 ), 428 piped = false, 429 latency = UncertainLatency(), 430 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 431 immType = Set(SelImm.IMM_S), 432 ) 433 434 val StdCfg: FuConfig = FuConfig ( 435 name = "std", 436 fuType = FuType.stu, 437 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 438 srcData = Seq( 439 Seq(IntData()), 440 Seq(FpData()), 441 ), 442 piped = true, 443 latency = CertainLatency(0) 444 ) 445 446 val MouCfg: FuConfig = FuConfig ( 447 name = "mou", 448 fuType = FuType.mou, 449 fuGen = null, // Todo 450 srcData = Seq( 451 Seq(IntData()), 452 ), 453 piped = false, // Todo: check it 454 writeIntRf = true, 455 latency = UncertainLatency(), 456 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct 457 ) 458 459 val MoudCfg: FuConfig = FuConfig ( 460 name = "moud", 461 fuType = FuType.mou, 462 fuGen = null, // Todo 463 srcData = Seq( 464 Seq(IntData()), 465 ), 466 piped = true, 467 latency = CertainLatency(0), 468 ) 469 470 val VialuCfg = FuConfig ( 471 name = "vialuFix", 472 fuType = FuType.vialuF, 473 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 474 srcData = Seq( 475 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 476 ), 477 piped = true, 478 writeVecRf = true, 479 writeVxsat = true, 480 latency = CertainLatency(1), 481 vconfigWakeUp = true, 482 maskWakeUp = true, 483 dataBits = 128, 484 exceptionOut = Seq(illegalInstr), 485 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 486 ) 487 488 val VimacCfg = FuConfig ( 489 name = "vimac", 490 fuType = FuType.vimac, 491 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 492 srcData = Seq( 493 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 494 ), 495 piped = true, 496 writeVecRf = true, 497 writeVxsat = true, 498 latency = CertainLatency(2), 499 vconfigWakeUp = true, 500 maskWakeUp = true, 501 dataBits = 128, 502 exceptionOut = Seq(illegalInstr), 503 ) 504 505 val VppuCfg = FuConfig ( 506 name = "vppu", 507 fuType = FuType.vppu, 508 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 509 srcData = Seq( 510 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 511 ), 512 piped = true, 513 writeVecRf = true, 514 writeVxsat = true, 515 latency = CertainLatency(1), 516 vconfigWakeUp = true, 517 maskWakeUp = true, 518 dataBits = 128, 519 exceptionOut = Seq(illegalInstr), 520 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 521 ) 522 523 val VipuCfg: FuConfig = FuConfig ( 524 name = "vipu", 525 fuType = FuType.vipu, 526 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 527 srcData = Seq( 528 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 529 ), 530 piped = true, 531 writeVecRf = true, 532 latency = CertainLatency(1), 533 vconfigWakeUp = true, 534 maskWakeUp = true, 535 dataBits = 128, 536 exceptionOut = Seq(illegalInstr), 537 ) 538 539 val VfaluCfg = FuConfig ( 540 name = "vfalu", 541 fuType = FuType.vfalu, 542 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 543 srcData = Seq( 544 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 545 ), 546 piped = true, 547 writeVecRf = true, 548 writeFpRf = true, 549 writeIntRf = true, 550 writeFflags = true, 551 latency = CertainLatency(1), 552 vconfigWakeUp = true, 553 maskWakeUp = true, 554 dataBits = 128, 555 exceptionOut = Seq(illegalInstr), 556 ) 557 558 val VfmaCfg = FuConfig ( 559 name = "vfma", 560 fuType = FuType.vfma, 561 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 562 srcData = Seq( 563 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 564 ), 565 piped = true, 566 writeVecRf = true, 567 writeFpRf = true, 568 writeFflags = true, 569 latency = CertainLatency(3), 570 vconfigWakeUp = true, 571 maskWakeUp = true, 572 dataBits = 128, 573 exceptionOut = Seq(illegalInstr), 574 ) 575 576 val VfdivCfg = FuConfig( 577 name = "vfdiv", 578 fuType = FuType.vfdiv, 579 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 580 srcData = Seq( 581 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 582 ), 583 piped = false, 584 writeVecRf = true, 585 writeFpRf = true, 586 writeFflags = true, 587 latency = UncertainLatency(), 588 vconfigWakeUp = true, 589 maskWakeUp = true, 590 dataBits = 128, 591 exceptionOut = Seq(illegalInstr), 592 ) 593 594 val VfcvtCfg = FuConfig( 595 name = "vfcvt", 596 fuType = FuType.vfcvt, 597 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 598 srcData = Seq( 599 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 600 ), 601 piped = true, 602 writeVecRf = true, 603 writeFpRf = false, 604 writeFflags = true, 605 latency = CertainLatency(2), 606 vconfigWakeUp = true, 607 maskWakeUp = true, 608 dataBits = 128, 609 exceptionOut = Seq(illegalInstr), 610 ) 611 612 613 val VlduCfg: FuConfig = FuConfig ( 614 name = "vldu", 615 fuType = FuType.vldu, 616 fuGen = null, 617 srcData = Seq( 618 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 619 ), 620 piped = false, // Todo: check it 621 writeVecRf = true, 622 latency = UncertainLatency(), 623 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 624 flushPipe = true, 625 replayInst = true, 626 hasLoadError = true, 627 vconfigWakeUp = true, 628 maskWakeUp = true, 629 dataBits = 128, 630 ) 631 //TODO 632 // def VstuCfg = FuConfig () 633 634 def allConfigs = Seq( 635 JmpCfg, BrhCfg, I2fCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 636 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, 637 VfaluCfg, VfmaCfg 638 ) 639 640 def VecArithFuConfigs = Seq( 641 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 642 ) 643} 644 645