1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 writeVConfig : Boolean = false, 67 writeVType : Boolean = false, 68 immType : Set[UInt] = Set(), 69 // vector 70 vconfigWakeUp : Boolean = false, 71 maskWakeUp : Boolean = false, 72) { 73 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 74 def needFpWen: Boolean = writeFpRf 75 def needVecWen: Boolean = writeVecRf 76 var vconfigIdx = -1 77 var maskSrcIdx = -1 78 if (vconfigWakeUp) { 79 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 80 } 81 if (maskWakeUp) { 82 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 83 } 84 85 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 86 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 87 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 88 89 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 94 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 95 96 def readFp: Boolean = numFpSrc > 0 97 98 def fuSel(uop: ExuInput): Bool = { 99 // Don't add more shit here!!! 100 // Todo: add new FuType to distinguish f2i, f2f 101 uop.fuType === this.fuType.U 102 } 103 104 /** 105 * params(i): data type set of the ith src port 106 * @return 107 */ 108 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 109 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 110 // make srcData is uniform sized to avoid exception when transpose 111 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 112 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 113 } 114 115 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 116 srcData 117 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 118 .filter(_.nonEmpty) 119 .map(_.get) 120 .toSet 121 } 122 123 def hasNoDataWB: Boolean = { 124 !(writeIntRf || writeFpRf || writeVecRf) 125 } 126 127 def getSrcMaxWidthVec = { 128 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 129 } 130 131 def genSrcDataVec: Seq[UInt] = { 132 getSrcMaxWidthVec.map(w => UInt(w.W)) 133 } 134 135 // csr's redirect is in its exception bundle 136 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 137 138 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 139 140 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 141 142 // predict info 143 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 144 145 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 146 147 def needFPUCtrl: Boolean = { 148 import FuType._ 149 Seq(fmac, fDivSqrt, i2f).contains(fuType) 150 } 151 152 def needVecCtrl: Boolean = { 153 import FuType._ 154 Seq(falu, fmac, fDivSqrt, fcvt, 155 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 156 } 157 158 def isMul: Boolean = fuType == FuType.mul 159 160 def isDiv: Boolean = fuType == FuType.div 161 162 def isCsr: Boolean = fuType == FuType.csr 163 164 def isFence: Boolean = fuType == FuType.fence 165 166 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 167 fuType == FuType.vppu || fuType == FuType.vipu || 168 fuType == FuType.vfalu || fuType == FuType.vfma || 169 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 170 fuType == FuType.vidiv 171 172 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 173 174 def isSta: Boolean = name.contains("sta") 175 176 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 177 fuType == FuType.div || fuType == FuType.fDivSqrt || 178 fuType == FuType.vfdiv || fuType == FuType.vidiv 179 180 /** 181 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 182 * @param data [[DataConfig]] 183 * @param tips tips if get failed 184 * @return the index of special src data 185 */ 186 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 187 val srcIdxVec = srcData.map(x => x.indexOf(data)) 188 val idx0 = srcIdxVec.head 189 for (idx <- srcIdxVec) { 190 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 191 } 192 idx0 193 } 194 195 override def toString: String = { 196 var str = s"${this.name}: " 197 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 198 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 199 str += s"latency($latency)" 200 str += s"src($srcData)" 201 str 202 } 203} 204 205object FuConfig { 206 val JmpCfg: FuConfig = FuConfig ( 207 name = "jmp", 208 fuType = FuType.jmp, 209 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 210 srcData = Seq( 211 Seq(IntData()), // jal 212 ), 213 piped = true, 214 writeIntRf = true, 215 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 216 ) 217 218 val BrhCfg: FuConfig = FuConfig ( 219 name = "brh", 220 fuType = FuType.brh, 221 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 222 srcData = Seq( 223 Seq(IntData(), IntData()), 224 ), 225 piped = true, 226 immType = Set(SelImm.IMM_SB), 227 ) 228 229 val I2fCfg: FuConfig = FuConfig ( 230 name = "i2f", 231 FuType.i2f, 232 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 233 srcData = Seq( 234 Seq(IntData()), 235 ), 236 piped = true, 237 writeFpRf = true, 238 writeFflags = true, 239 latency = CertainLatency(2), 240 needSrcFrm = true, 241 ) 242 243 val I2vCfg: FuConfig = FuConfig ( 244 name = "i2v", 245 FuType.i2v, 246 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 247 srcData = Seq( 248 Seq(IntData(), IntData()), 249 ), 250 piped = true, 251 writeFpRf = true, 252 writeVecRf = true, 253 latency = CertainLatency(0), 254 dataBits = 128, 255 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 256 ) 257 258 val F2vCfg: FuConfig = FuConfig ( 259 name = "f2v", 260 FuType.f2v, 261 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 262 srcData = Seq( 263 Seq(FpData(), FpData()), 264 Seq(FpData()), 265 ), 266 piped = true, 267 writeVecRf = true, 268 latency = CertainLatency(0), 269 dataBits = 128, 270 ) 271 272 val CsrCfg: FuConfig = FuConfig ( 273 name = "csr", 274 fuType = FuType.csr, 275 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 276 srcData = Seq( 277 Seq(IntData()), 278 ), 279 piped = true, 280 writeIntRf = true, 281 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 282 flushPipe = true, 283 ) 284 285 val AluCfg: FuConfig = FuConfig ( 286 name = "alu", 287 fuType = FuType.alu, 288 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 289 srcData = Seq( 290 Seq(IntData(), IntData()), 291 ), 292 piped = true, 293 writeIntRf = true, 294 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 295 ) 296 297 val MulCfg: FuConfig = FuConfig ( 298 name = "mul", 299 fuType = FuType.mul, 300 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 301 srcData = Seq( 302 Seq(IntData(), IntData()), 303 ), 304 piped = true, 305 writeIntRf = true, 306 latency = CertainLatency(2), 307 ) 308 309 val DivCfg: FuConfig = FuConfig ( 310 name = "div", 311 fuType = FuType.div, 312 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 313 srcData = Seq( 314 Seq(IntData(), IntData()), 315 ), 316 piped = false, 317 writeIntRf = true, 318 latency = UncertainLatency(), 319 hasInputBuffer = (true, 4, true) 320 ) 321 322 val FenceCfg: FuConfig = FuConfig ( 323 name = "fence", 324 FuType.fence, 325 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 326 srcData = Seq( 327 Seq(IntData(), IntData()), 328 ), 329 piped = true, 330 latency = CertainLatency(0), 331 exceptionOut = Seq(illegalInstr, virtualInstr), 332 flushPipe = true 333 ) 334 335 // Todo: split it to simple bitmap exu and complex bku 336 val BkuCfg: FuConfig = FuConfig ( 337 name = "bku", 338 fuType = FuType.bku, 339 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 340 srcData = Seq( 341 Seq(IntData(), IntData()), 342 ), 343 piped = true, 344 writeIntRf = true, 345 latency = CertainLatency(2), 346 ) 347 348 val VSetRvfWvfCfg: FuConfig = FuConfig( 349 name = "vsetrvfwvf", 350 fuType = FuType.vsetfwf, 351 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 352 srcData = Seq( 353 Seq(VecData(), VecData()), 354 ), 355 piped = true, 356 writeVecRf = true, 357 writeVConfig = true, 358 writeVType = true, 359 latency = CertainLatency(0), 360 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 361 ) 362 363 val VSetRiWvfCfg: FuConfig = FuConfig( 364 name = "vsetriwvf", 365 fuType = FuType.vsetiwf, 366 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 367 srcData = Seq( 368 Seq(IntData(), IntData()), 369 ), 370 piped = true, 371 writeVecRf = true, 372 writeVConfig = true, 373 writeVType = true, 374 latency = CertainLatency(0), 375 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 376 ) 377 378 val VSetRiWiCfg: FuConfig = FuConfig( 379 name = "vsetriwi", 380 fuType = FuType.vsetiwi, 381 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 382 srcData = Seq( 383 Seq(IntData(), IntData()), 384 ), 385 piped = true, 386 writeIntRf = true, 387 latency = CertainLatency(0), 388 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 389 ) 390 391 val LduCfg: FuConfig = FuConfig ( 392 name = "ldu", 393 fuType = FuType.ldu, 394 fuGen = null, // Todo 395 srcData = Seq( 396 Seq(IntData()), 397 ), 398 piped = false, // Todo: check it 399 writeIntRf = true, 400 writeFpRf = true, 401 latency = UncertainLatency(3), 402 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 403 flushPipe = true, 404 replayInst = true, 405 hasLoadError = true, 406 trigger = true, 407 immType = Set(SelImm.IMM_I), 408 ) 409 410 val StaCfg: FuConfig = FuConfig ( 411 name = "sta", 412 fuType = FuType.stu, 413 fuGen = null, // Todo 414 srcData = Seq( 415 Seq(IntData()), 416 ), 417 piped = false, 418 latency = UncertainLatency(), 419 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 420 trigger = true, 421 immType = Set(SelImm.IMM_S), 422 ) 423 424 val StdCfg: FuConfig = FuConfig ( 425 name = "std", 426 fuType = FuType.stu, 427 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 428 srcData = Seq( 429 Seq(IntData()), 430 Seq(FpData()), 431 ), 432 piped = true, 433 latency = CertainLatency(0) 434 ) 435 436 val HyldaCfg = FuConfig ( 437 name = "hylda", 438 fuType = FuType.ldu, 439 fuGen = null, // Todo 440 srcData = Seq( 441 Seq(IntData()), 442 ), 443 piped = false, // Todo: check it 444 writeIntRf = true, 445 writeFpRf = true, 446 latency = UncertainLatency(3), 447 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 448 flushPipe = true, 449 replayInst = true, 450 hasLoadError = true, 451 immType = Set(SelImm.IMM_I), 452 ) 453 454 val HystaCfg = FuConfig ( 455 name = "hysta", 456 fuType = FuType.stu, 457 fuGen = null, // Todo 458 srcData = Seq( 459 Seq(IntData()), 460 ), 461 piped = false, 462 latency = UncertainLatency(), 463 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 464 immType = Set(SelImm.IMM_S), 465 ) 466 467 val FakeHystaCfg = FuConfig ( 468 name = "hysta", 469 fuType = FuType.stu, 470 fuGen = null, // Todo 471 srcData = Seq(), 472 piped = false, 473 latency = UncertainLatency(), 474 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 475 immType = Set(), 476 ) 477 478 val MouCfg: FuConfig = FuConfig ( 479 name = "mou", 480 fuType = FuType.mou, 481 fuGen = null, // Todo 482 srcData = Seq( 483 Seq(IntData()), 484 ), 485 piped = false, // Todo: check it 486 writeFakeIntRf = true, 487 latency = UncertainLatency(), 488 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 489 trigger = true, 490 ) 491 492 val MoudCfg: FuConfig = FuConfig ( 493 name = "moud", 494 fuType = FuType.mou, 495 fuGen = null, // Todo 496 srcData = Seq( 497 Seq(IntData()), 498 ), 499 piped = true, 500 latency = CertainLatency(0), 501 ) 502 503 val VialuCfg = FuConfig ( 504 name = "vialuFix", 505 fuType = FuType.vialuF, 506 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 507 srcData = Seq( 508 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 509 ), 510 piped = true, 511 writeVecRf = true, 512 writeVxsat = true, 513 needSrcVxrm = true, 514 latency = CertainLatency(1), 515 vconfigWakeUp = true, 516 maskWakeUp = true, 517 dataBits = 128, 518 exceptionOut = Seq(illegalInstr), 519 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 520 ) 521 522 val VimacCfg = FuConfig ( 523 name = "vimac", 524 fuType = FuType.vimac, 525 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 526 srcData = Seq( 527 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 528 ), 529 piped = true, 530 writeVecRf = true, 531 writeVxsat = true, 532 needSrcVxrm = true, 533 latency = CertainLatency(2), 534 vconfigWakeUp = true, 535 maskWakeUp = true, 536 dataBits = 128, 537 exceptionOut = Seq(illegalInstr), 538 ) 539 540 val VidivCfg = FuConfig ( 541 name = "vidiv", 542 fuType = FuType.vidiv, 543 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 544 srcData = Seq( 545 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 546 ), 547 piped = false, 548 writeVecRf = true, 549 latency = UncertainLatency(), 550 vconfigWakeUp = true, 551 maskWakeUp = true, 552 dataBits = 128, 553 exceptionOut = Seq(illegalInstr), 554 ) 555 556 val VppuCfg = FuConfig ( 557 name = "vppu", 558 fuType = FuType.vppu, 559 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 560 srcData = Seq( 561 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 562 ), 563 piped = true, 564 writeVecRf = true, 565 latency = CertainLatency(2), 566 vconfigWakeUp = true, 567 maskWakeUp = true, 568 dataBits = 128, 569 exceptionOut = Seq(illegalInstr), 570 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 571 ) 572 573 val VipuCfg: FuConfig = FuConfig ( 574 name = "vipu", 575 fuType = FuType.vipu, 576 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 577 srcData = Seq( 578 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 579 ), 580 piped = true, 581 writeIntRf = true, 582 writeVecRf = true, 583 latency = CertainLatency(2), 584 vconfigWakeUp = true, 585 maskWakeUp = true, 586 dataBits = 128, 587 exceptionOut = Seq(illegalInstr), 588 ) 589 590 val VfaluCfg = FuConfig ( 591 name = "vfalu", 592 fuType = FuType.vfalu, 593 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 594 srcData = Seq( 595 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 596 ), 597 piped = true, 598 writeVecRf = true, 599 writeFpRf = true, 600 writeIntRf = true, 601 writeFflags = true, 602 latency = CertainLatency(1), 603 vconfigWakeUp = true, 604 maskWakeUp = true, 605 dataBits = 128, 606 exceptionOut = Seq(illegalInstr), 607 needSrcFrm = true, 608 ) 609 610 val VfmaCfg = FuConfig ( 611 name = "vfma", 612 fuType = FuType.vfma, 613 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 614 srcData = Seq( 615 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 616 ), 617 piped = true, 618 writeVecRf = true, 619 writeFflags = true, 620 latency = CertainLatency(3), 621 vconfigWakeUp = true, 622 maskWakeUp = true, 623 dataBits = 128, 624 exceptionOut = Seq(illegalInstr), 625 needSrcFrm = true, 626 ) 627 628 val VfdivCfg = FuConfig( 629 name = "vfdiv", 630 fuType = FuType.vfdiv, 631 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 632 srcData = Seq( 633 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 634 ), 635 piped = false, 636 writeVecRf = true, 637 writeFflags = true, 638 latency = UncertainLatency(), 639 vconfigWakeUp = true, 640 maskWakeUp = true, 641 dataBits = 128, 642 exceptionOut = Seq(illegalInstr), 643 needSrcFrm = true, 644 ) 645 646 val VfcvtCfg = FuConfig( 647 name = "vfcvt", 648 fuType = FuType.vfcvt, 649 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 650 srcData = Seq( 651 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 652 ), 653 piped = true, 654 writeVecRf = true, 655 writeIntRf = true, 656 writeFflags = true, 657 latency = CertainLatency(2), 658 vconfigWakeUp = true, 659 maskWakeUp = true, 660 dataBits = 128, 661 exceptionOut = Seq(illegalInstr), 662 needSrcFrm = true, 663 ) 664 665 val FaluCfg = FuConfig( 666 name = "falu", 667 fuType = FuType.falu, 668 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 669 srcData = Seq( 670 Seq(FpData(), FpData()), 671 ), 672 piped = true, 673 writeFpRf = true, 674 writeIntRf = true, 675 writeFflags = true, 676 latency = CertainLatency(1), 677 dataBits = 64, 678 needSrcFrm = true, 679 ) 680 681 val FmacCfg = FuConfig( 682 name = "fmac", 683 fuType = FuType.fmac, 684 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 685 srcData = Seq( 686 Seq(FpData(), FpData(), FpData()), 687 ), 688 piped = true, 689 writeFpRf = true, 690 writeFflags = true, 691 latency = CertainLatency(3), 692 dataBits = 64, 693 needSrcFrm = true, 694 ) 695 696 val FdivCfg = FuConfig( 697 name = "fdiv", 698 fuType = FuType.fDivSqrt, 699 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 700 srcData = Seq( 701 Seq(FpData(), FpData()), 702 ), 703 piped = false, 704 writeFpRf = true, 705 writeFflags = true, 706 latency = UncertainLatency(), 707 dataBits = 64, 708 needSrcFrm = true, 709 ) 710 711 val FcvtCfg = FuConfig( 712 name = "fcvt", 713 fuType = FuType.fcvt, 714 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 715 srcData = Seq( 716 Seq(FpData()), 717 ), 718 piped = true, 719 writeFpRf = true, 720 writeIntRf = true, 721 writeFflags = true, 722 latency = CertainLatency(2), 723 dataBits = 64, 724 needSrcFrm = true, 725 ) 726 727 val VlduCfg: FuConfig = FuConfig ( 728 name = "vldu", 729 fuType = FuType.vldu, 730 fuGen = null, 731 srcData = Seq( 732 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 733 ), 734 piped = false, // Todo: check it 735 writeVecRf = true, 736 latency = UncertainLatency(), 737 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 738 flushPipe = true, 739 replayInst = true, 740 hasLoadError = true, 741 vconfigWakeUp = true, 742 maskWakeUp = true, 743 dataBits = 128, 744 ) 745 746 val VstuCfg: FuConfig = FuConfig ( 747 name = "vstu", 748 fuType = FuType.vstu, 749 fuGen = null, 750 srcData = Seq( 751 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 752 ), 753 piped = false, 754 writeVecRf = false, 755 latency = UncertainLatency(), 756 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 757 flushPipe = true, 758 replayInst = true, 759 hasLoadError = true, 760 vconfigWakeUp = true, 761 maskWakeUp = true, 762 dataBits = 128, 763 ) 764 765 val VseglduSeg: FuConfig = FuConfig ( 766 name = "vsegldu", 767 fuType = FuType.vsegldu, 768 fuGen = null, 769 srcData = Seq( 770 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 771 ), 772 piped = false, // Todo: check it 773 writeVecRf = true, 774 latency = UncertainLatency(), 775 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 776 flushPipe = true, 777 replayInst = true, 778 hasLoadError = true, 779 vconfigWakeUp = true, 780 maskWakeUp = true, 781 dataBits = 128, 782 ) 783 784 val VsegstuCfg: FuConfig = FuConfig( 785 name = "vsegstu", 786 fuType = FuType.vsegstu, 787 fuGen = null, 788 srcData = Seq( 789 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 790 ), 791 piped = false, 792 writeVecRf = false, 793 latency = UncertainLatency(), 794 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 795 flushPipe = true, 796 replayInst = true, 797 hasLoadError = true, 798 vconfigWakeUp = true, 799 maskWakeUp = true, 800 dataBits = 128, 801 ) 802 803 def allConfigs = Seq( 804 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 805 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 806 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 807 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 808 ) 809 810 def VecArithFuConfigs = Seq( 811 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 812 ) 813} 814 815