1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 writeVType : Boolean = false, 67 immType : Set[UInt] = Set(), 68 // vector 69 vconfigWakeUp : Boolean = false, 70 maskWakeUp : Boolean = false, 71) { 72 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 73 def needFpWen: Boolean = writeFpRf 74 def needVecWen: Boolean = writeVecRf 75 var vconfigIdx = -1 76 var maskSrcIdx = -1 77 if (vconfigWakeUp) { 78 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 79 } 80 if (maskWakeUp) { 81 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 82 } 83 84 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 85 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 86 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 87 88 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 94 95 def readFp: Boolean = numFpSrc > 0 96 97 def fuSel(uop: ExuInput): Bool = { 98 // Don't add more shit here!!! 99 // Todo: add new FuType to distinguish f2i, f2f 100 uop.fuType === this.fuType.U 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 138 139 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 140 141 // predict info 142 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 145 146 def needFPUCtrl: Boolean = { 147 import FuType._ 148 Seq(fmac, fDivSqrt, i2f).contains(fuType) 149 } 150 151 def needVecCtrl: Boolean = { 152 import FuType._ 153 Seq(falu, fmac, fDivSqrt, fcvt, 154 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 155 } 156 157 def isMul: Boolean = fuType == FuType.mul 158 159 def isDiv: Boolean = fuType == FuType.div 160 161 def isCsr: Boolean = fuType == FuType.csr 162 163 def isFence: Boolean = fuType == FuType.fence 164 165 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 166 fuType == FuType.vppu || fuType == FuType.vipu || 167 fuType == FuType.vfalu || fuType == FuType.vfma || 168 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 169 fuType == FuType.vidiv 170 171 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 172 173 def isSta: Boolean = name.contains("sta") 174 175 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 176 fuType == FuType.div || 177 fuType == FuType.vfdiv || fuType == FuType.vidiv 178 179 /** 180 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 181 * @param data [[DataConfig]] 182 * @param tips tips if get failed 183 * @return the index of special src data 184 */ 185 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 186 val srcIdxVec = srcData.map(x => x.indexOf(data)) 187 val idx0 = srcIdxVec.head 188 for (idx <- srcIdxVec) { 189 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 190 } 191 idx0 192 } 193 194 override def toString: String = { 195 var str = s"${this.name}: " 196 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 197 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 198 str += s"latency($latency)" 199 str += s"src($srcData)" 200 str 201 } 202} 203 204object FuConfig { 205 val JmpCfg: FuConfig = FuConfig ( 206 name = "jmp", 207 fuType = FuType.jmp, 208 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 209 srcData = Seq( 210 Seq(IntData()), // jal 211 ), 212 piped = true, 213 writeIntRf = true, 214 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 215 ) 216 217 val BrhCfg: FuConfig = FuConfig ( 218 name = "brh", 219 fuType = FuType.brh, 220 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 221 srcData = Seq( 222 Seq(IntData(), IntData()), 223 ), 224 piped = true, 225 immType = Set(SelImm.IMM_SB), 226 ) 227 228 val I2fCfg: FuConfig = FuConfig ( 229 name = "i2f", 230 FuType.i2f, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 232 srcData = Seq( 233 Seq(IntData()), 234 ), 235 piped = true, 236 writeFpRf = true, 237 writeFflags = true, 238 latency = CertainLatency(2), 239 needSrcFrm = true, 240 ) 241 242 val I2vCfg: FuConfig = FuConfig ( 243 name = "i2v", 244 FuType.i2v, 245 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 246 srcData = Seq( 247 Seq(IntData(), IntData()), 248 ), 249 piped = true, 250 writeVecRf = true, 251 latency = CertainLatency(0), 252 dataBits = 128, 253 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 254 ) 255 256 val F2vCfg: FuConfig = FuConfig ( 257 name = "f2v", 258 FuType.f2v, 259 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 260 srcData = Seq( 261 Seq(FpData(), FpData()), 262 Seq(FpData()), 263 ), 264 piped = true, 265 writeVecRf = true, 266 latency = CertainLatency(0), 267 dataBits = 128, 268 ) 269 270 val CsrCfg: FuConfig = FuConfig ( 271 name = "csr", 272 fuType = FuType.csr, 273 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 274 srcData = Seq( 275 Seq(IntData()), 276 ), 277 piped = true, 278 writeIntRf = true, 279 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 280 flushPipe = true, 281 ) 282 283 val AluCfg: FuConfig = FuConfig ( 284 name = "alu", 285 fuType = FuType.alu, 286 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 287 srcData = Seq( 288 Seq(IntData(), IntData()), 289 ), 290 piped = true, 291 writeIntRf = true, 292 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 293 ) 294 295 val MulCfg: FuConfig = FuConfig ( 296 name = "mul", 297 fuType = FuType.mul, 298 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 299 srcData = Seq( 300 Seq(IntData(), IntData()), 301 ), 302 piped = true, 303 writeIntRf = true, 304 latency = CertainLatency(2), 305 ) 306 307 val DivCfg: FuConfig = FuConfig ( 308 name = "div", 309 fuType = FuType.div, 310 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 311 srcData = Seq( 312 Seq(IntData(), IntData()), 313 ), 314 piped = false, 315 writeIntRf = true, 316 latency = UncertainLatency(), 317 hasInputBuffer = (true, 4, true) 318 ) 319 320 val FenceCfg: FuConfig = FuConfig ( 321 name = "fence", 322 FuType.fence, 323 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 324 srcData = Seq( 325 Seq(IntData(), IntData()), 326 ), 327 piped = true, 328 latency = CertainLatency(0), 329 exceptionOut = Seq(illegalInstr, virtualInstr), 330 flushPipe = true 331 ) 332 333 // Todo: split it to simple bitmap exu and complex bku 334 val BkuCfg: FuConfig = FuConfig ( 335 name = "bku", 336 fuType = FuType.bku, 337 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 338 srcData = Seq( 339 Seq(IntData(), IntData()), 340 ), 341 piped = true, 342 writeIntRf = true, 343 latency = CertainLatency(2), 344 ) 345 346 val VSetRvfWvfCfg: FuConfig = FuConfig( 347 name = "vsetrvfwvf", 348 fuType = FuType.vsetfwf, 349 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 350 srcData = Seq( 351 Seq(FpData(), FpData()), 352 ), 353 piped = true, 354 writeVecRf = true, 355 writeVType = true, 356 latency = CertainLatency(0), 357 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 358 ) 359 360 val VSetRiWvfCfg: FuConfig = FuConfig( 361 name = "vsetriwvf", 362 fuType = FuType.vsetiwf, 363 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 364 srcData = Seq( 365 Seq(IntData(), IntData()), 366 ), 367 piped = true, 368 writeVecRf = true, 369 writeVType = true, 370 latency = CertainLatency(0), 371 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 372 ) 373 374 val VSetRiWiCfg: FuConfig = FuConfig( 375 name = "vsetriwi", 376 fuType = FuType.vsetiwi, 377 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 378 srcData = Seq( 379 Seq(IntData(), IntData()), 380 ), 381 piped = true, 382 writeIntRf = true, 383 latency = CertainLatency(0), 384 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 385 ) 386 387 val FDivSqrtCfg: FuConfig = FuConfig ( 388 name = "fDivSqrt", 389 fuType = FuType.fDivSqrt, 390 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 391 srcData = Seq( 392 Seq(FpData(), FpData()), 393 ), 394 piped = false, 395 writeFpRf = true, 396 writeFflags = true, 397 latency = UncertainLatency(), 398 hasInputBuffer = (true, 8, true), 399 needSrcFrm = true, 400 ) 401 402 val LduCfg: FuConfig = FuConfig ( 403 name = "ldu", 404 fuType = FuType.ldu, 405 fuGen = null, // Todo 406 srcData = Seq( 407 Seq(IntData()), 408 ), 409 piped = false, // Todo: check it 410 writeIntRf = true, 411 writeFpRf = true, 412 latency = UncertainLatency(3), 413 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 414 flushPipe = true, 415 replayInst = true, 416 hasLoadError = true, 417 trigger = true, 418 immType = Set(SelImm.IMM_I), 419 ) 420 421 val StaCfg: FuConfig = FuConfig ( 422 name = "sta", 423 fuType = FuType.stu, 424 fuGen = null, // Todo 425 srcData = Seq( 426 Seq(IntData()), 427 ), 428 piped = false, 429 latency = UncertainLatency(), 430 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 431 trigger = true, 432 immType = Set(SelImm.IMM_S), 433 ) 434 435 val StdCfg: FuConfig = FuConfig ( 436 name = "std", 437 fuType = FuType.stu, 438 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 439 srcData = Seq( 440 Seq(IntData()), 441 Seq(FpData()), 442 ), 443 piped = true, 444 latency = CertainLatency(0) 445 ) 446 447 val HyldaCfg = FuConfig ( 448 name = "hylda", 449 fuType = FuType.ldu, 450 fuGen = null, // Todo 451 srcData = Seq( 452 Seq(IntData()), 453 ), 454 piped = false, // Todo: check it 455 writeIntRf = true, 456 writeFpRf = true, 457 latency = UncertainLatency(3), 458 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 459 flushPipe = true, 460 replayInst = true, 461 hasLoadError = true, 462 immType = Set(SelImm.IMM_I), 463 ) 464 465 val HystaCfg = FuConfig ( 466 name = "hysta", 467 fuType = FuType.stu, 468 fuGen = null, // Todo 469 srcData = Seq( 470 Seq(IntData()), 471 ), 472 piped = false, 473 latency = UncertainLatency(), 474 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 475 immType = Set(SelImm.IMM_S), 476 ) 477 478 val FakeHystaCfg = FuConfig ( 479 name = "hysta", 480 fuType = FuType.stu, 481 fuGen = null, // Todo 482 srcData = Seq(), 483 piped = false, 484 latency = UncertainLatency(), 485 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 486 immType = Set(), 487 ) 488 489 val MouCfg: FuConfig = FuConfig ( 490 name = "mou", 491 fuType = FuType.mou, 492 fuGen = null, // Todo 493 srcData = Seq( 494 Seq(IntData()), 495 ), 496 piped = false, // Todo: check it 497 writeFakeIntRf = true, 498 latency = UncertainLatency(), 499 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 500 trigger = true, 501 ) 502 503 val MoudCfg: FuConfig = FuConfig ( 504 name = "moud", 505 fuType = FuType.mou, 506 fuGen = null, // Todo 507 srcData = Seq( 508 Seq(IntData()), 509 ), 510 piped = true, 511 latency = CertainLatency(0), 512 ) 513 514 val VialuCfg = FuConfig ( 515 name = "vialuFix", 516 fuType = FuType.vialuF, 517 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 518 srcData = Seq( 519 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 520 ), 521 piped = true, 522 writeVecRf = true, 523 writeVxsat = true, 524 needSrcVxrm = true, 525 latency = CertainLatency(1), 526 vconfigWakeUp = true, 527 maskWakeUp = true, 528 dataBits = 128, 529 exceptionOut = Seq(illegalInstr), 530 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 531 ) 532 533 val VimacCfg = FuConfig ( 534 name = "vimac", 535 fuType = FuType.vimac, 536 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 537 srcData = Seq( 538 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 539 ), 540 piped = true, 541 writeVecRf = true, 542 writeVxsat = true, 543 needSrcVxrm = true, 544 latency = CertainLatency(2), 545 vconfigWakeUp = true, 546 maskWakeUp = true, 547 dataBits = 128, 548 exceptionOut = Seq(illegalInstr), 549 ) 550 551 val VidivCfg = FuConfig ( 552 name = "vidiv", 553 fuType = FuType.vidiv, 554 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 555 srcData = Seq( 556 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 557 ), 558 piped = false, 559 writeVecRf = true, 560 latency = UncertainLatency(), 561 vconfigWakeUp = true, 562 maskWakeUp = true, 563 dataBits = 128, 564 exceptionOut = Seq(illegalInstr), 565 ) 566 567 val VppuCfg = FuConfig ( 568 name = "vppu", 569 fuType = FuType.vppu, 570 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 571 srcData = Seq( 572 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 573 ), 574 piped = true, 575 writeVecRf = true, 576 latency = CertainLatency(2), 577 vconfigWakeUp = true, 578 maskWakeUp = true, 579 dataBits = 128, 580 exceptionOut = Seq(illegalInstr), 581 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 582 ) 583 584 val VipuCfg: FuConfig = FuConfig ( 585 name = "vipu", 586 fuType = FuType.vipu, 587 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 588 srcData = Seq( 589 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 590 ), 591 piped = true, 592 writeIntRf = true, 593 writeVecRf = true, 594 latency = CertainLatency(2), 595 vconfigWakeUp = true, 596 maskWakeUp = true, 597 dataBits = 128, 598 exceptionOut = Seq(illegalInstr), 599 ) 600 601 val VfaluCfg = FuConfig ( 602 name = "vfalu", 603 fuType = FuType.vfalu, 604 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 605 srcData = Seq( 606 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 607 ), 608 piped = true, 609 writeVecRf = true, 610 writeIntRf = true, 611 writeFflags = true, 612 latency = CertainLatency(1), 613 vconfigWakeUp = true, 614 maskWakeUp = true, 615 dataBits = 128, 616 exceptionOut = Seq(illegalInstr), 617 needSrcFrm = true, 618 ) 619 620 val VfmaCfg = FuConfig ( 621 name = "vfma", 622 fuType = FuType.vfma, 623 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 624 srcData = Seq( 625 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 626 ), 627 piped = true, 628 writeVecRf = true, 629 writeFflags = true, 630 latency = CertainLatency(3), 631 vconfigWakeUp = true, 632 maskWakeUp = true, 633 dataBits = 128, 634 exceptionOut = Seq(illegalInstr), 635 needSrcFrm = true, 636 ) 637 638 val VfdivCfg = FuConfig( 639 name = "vfdiv", 640 fuType = FuType.vfdiv, 641 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 642 srcData = Seq( 643 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 644 ), 645 piped = false, 646 writeVecRf = true, 647 writeFflags = true, 648 latency = UncertainLatency(), 649 vconfigWakeUp = true, 650 maskWakeUp = true, 651 dataBits = 128, 652 exceptionOut = Seq(illegalInstr), 653 needSrcFrm = true, 654 ) 655 656 val VfcvtCfg = FuConfig( 657 name = "vfcvt", 658 fuType = FuType.vfcvt, 659 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 660 srcData = Seq( 661 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 662 ), 663 piped = true, 664 writeVecRf = true, 665 writeIntRf = true, 666 writeFflags = true, 667 latency = CertainLatency(2), 668 vconfigWakeUp = true, 669 maskWakeUp = true, 670 dataBits = 128, 671 exceptionOut = Seq(illegalInstr), 672 needSrcFrm = true, 673 ) 674 675 val FaluCfg = FuConfig( 676 name = "falu", 677 fuType = FuType.falu, 678 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 679 srcData = Seq( 680 Seq(FpData(), FpData()), 681 ), 682 piped = true, 683 writeFpRf = true, 684 writeIntRf = true, 685 writeFflags = true, 686 latency = CertainLatency(1), 687 dataBits = 64, 688 needSrcFrm = true, 689 ) 690 691 val FmacCfg = FuConfig( 692 name = "fmac", 693 fuType = FuType.fmac, 694 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 695 srcData = Seq( 696 Seq(FpData(), FpData(), FpData()), 697 ), 698 piped = true, 699 writeFpRf = true, 700 writeFflags = true, 701 latency = CertainLatency(3), 702 dataBits = 64, 703 needSrcFrm = true, 704 ) 705 706 val FdivCfg = FuConfig( 707 name = "fdiv", 708 fuType = FuType.fDivSqrt, 709 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 710 srcData = Seq( 711 Seq(FpData(), FpData()), 712 ), 713 piped = false, 714 writeFpRf = true, 715 writeFflags = true, 716 latency = UncertainLatency(), 717 dataBits = 64, 718 needSrcFrm = true, 719 ) 720 721 val FcvtCfg = FuConfig( 722 name = "fcvt", 723 fuType = FuType.fcvt, 724 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 725 srcData = Seq( 726 Seq(FpData()), 727 ), 728 piped = true, 729 writeFpRf = true, 730 writeIntRf = true, 731 writeFflags = true, 732 latency = CertainLatency(2), 733 dataBits = 64, 734 needSrcFrm = true, 735 ) 736 737 val VlduCfg: FuConfig = FuConfig ( 738 name = "vldu", 739 fuType = FuType.vldu, 740 fuGen = null, 741 srcData = Seq( 742 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 743 ), 744 piped = false, // Todo: check it 745 writeVecRf = true, 746 latency = UncertainLatency(), 747 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 748 flushPipe = true, 749 replayInst = true, 750 hasLoadError = true, 751 vconfigWakeUp = true, 752 maskWakeUp = true, 753 dataBits = 128, 754 ) 755 756 val VstuCfg: FuConfig = FuConfig ( 757 name = "vstu", 758 fuType = FuType.vstu, 759 fuGen = null, 760 srcData = Seq( 761 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 762 ), 763 piped = false, 764 writeVecRf = false, 765 latency = UncertainLatency(), 766 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 767 flushPipe = true, 768 replayInst = true, 769 hasLoadError = true, 770 vconfigWakeUp = true, 771 maskWakeUp = true, 772 dataBits = 128, 773 ) 774 775 def allConfigs = Seq( 776 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 777 FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 778 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 779 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 780 ) 781 782 def VecArithFuConfigs = Seq( 783 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 784 ) 785} 786 787