1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0), 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 writeVConfig : Boolean = false, 67 immType : Set[UInt] = Set(), 68 // vector 69 vconfigWakeUp : Boolean = false, 70 maskWakeUp : Boolean = false, 71) { 72 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 73 def needFpWen: Boolean = writeFpRf 74 def needVecWen: Boolean = writeVecRf 75 var vconfigIdx = -1 76 var maskSrcIdx = -1 77 if (vconfigWakeUp) { 78 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 79 } 80 if (maskWakeUp) { 81 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 82 } 83 84 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 85 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 86 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 87 88 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 94 95 def readFp: Boolean = numFpSrc > 0 96 97 def fuSel(uop: ExuInput): Bool = { 98 // Don't add more shit here!!! 99 // Todo: add new FuType to distinguish f2i, f2f 100 uop.fuType === this.fuType.U 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 138 139 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 140 141 // predict info 142 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 145 146 def needFPUCtrl: Boolean = { 147 import FuType._ 148 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 149 } 150 151 def needVecCtrl: Boolean = { 152 import FuType._ 153 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 154 } 155 156 def isMul: Boolean = fuType == FuType.mul 157 158 def isDiv: Boolean = fuType == FuType.div 159 160 def isCsr: Boolean = fuType == FuType.csr 161 162 def isFence: Boolean = fuType == FuType.fence 163 164 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 165 fuType == FuType.vppu || fuType == FuType.vipu || 166 fuType == FuType.vfalu || fuType == FuType.vfma || 167 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 168 fuType == FuType.vidiv 169 170 def isSta: Boolean = name.contains("sta") 171 172 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 173 fuType == FuType.fmisc || fuType == FuType.div || 174 fuType == FuType.vfdiv || fuType == FuType.vidiv 175 176 /** 177 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 178 * @param data [[DataConfig]] 179 * @param tips tips if get failed 180 * @return the index of special src data 181 */ 182 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 183 val srcIdxVec = srcData.map(x => x.indexOf(data)) 184 val idx0 = srcIdxVec.head 185 for (idx <- srcIdxVec) { 186 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 187 } 188 idx0 189 } 190 191 override def toString: String = { 192 var str = s"${this.name}: " 193 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 194 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 195 str += s"latency($latency)" 196 str += s"src($srcData)" 197 str 198 } 199} 200 201object FuConfig { 202 val JmpCfg: FuConfig = FuConfig ( 203 name = "jmp", 204 fuType = FuType.jmp, 205 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 206 srcData = Seq( 207 Seq(IntData()), // jal 208 ), 209 piped = true, 210 writeIntRf = true, 211 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 212 ) 213 214 val BrhCfg: FuConfig = FuConfig ( 215 name = "brh", 216 fuType = FuType.brh, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 218 srcData = Seq( 219 Seq(IntData(), IntData()), 220 ), 221 piped = true, 222 immType = Set(SelImm.IMM_SB), 223 ) 224 225 val I2fCfg: FuConfig = FuConfig ( 226 name = "i2f", 227 FuType.i2f, 228 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 229 srcData = Seq( 230 Seq(IntData()), 231 ), 232 piped = true, 233 writeFpRf = true, 234 writeFflags = true, 235 latency = CertainLatency(2), 236 needSrcFrm = true, 237 ) 238 239 val I2vCfg: FuConfig = FuConfig ( 240 name = "i2v", 241 FuType.i2v, 242 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 243 srcData = Seq( 244 Seq(IntData(), IntData()), 245 ), 246 piped = true, 247 writeVecRf = true, 248 writeFpRf = true, 249 latency = CertainLatency(0), 250 dataBits = 128, 251 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 252 ) 253 254 val F2vCfg: FuConfig = FuConfig ( 255 name = "f2v", 256 FuType.f2v, 257 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 258 srcData = Seq( 259 Seq(FpData(), FpData()), 260 Seq(FpData()), 261 ), 262 piped = true, 263 writeVecRf = true, 264 latency = CertainLatency(0), 265 dataBits = 128, 266 ) 267 268 val CsrCfg: FuConfig = FuConfig ( 269 name = "csr", 270 fuType = FuType.csr, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 272 srcData = Seq( 273 Seq(IntData()), 274 ), 275 piped = true, 276 writeIntRf = true, 277 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 278 flushPipe = true, 279 ) 280 281 val AluCfg: FuConfig = FuConfig ( 282 name = "alu", 283 fuType = FuType.alu, 284 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 285 srcData = Seq( 286 Seq(IntData(), IntData()), 287 ), 288 piped = true, 289 writeIntRf = true, 290 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 291 ) 292 293 val MulCfg: FuConfig = FuConfig ( 294 name = "mul", 295 fuType = FuType.mul, 296 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 297 srcData = Seq( 298 Seq(IntData(), IntData()), 299 ), 300 piped = true, 301 writeIntRf = true, 302 latency = CertainLatency(2), 303 ) 304 305 val DivCfg: FuConfig = FuConfig ( 306 name = "div", 307 fuType = FuType.div, 308 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 309 srcData = Seq( 310 Seq(IntData(), IntData()), 311 ), 312 piped = false, 313 writeIntRf = true, 314 latency = UncertainLatency(), 315 hasInputBuffer = (true, 4, true) 316 ) 317 318 val FenceCfg: FuConfig = FuConfig ( 319 name = "fence", 320 FuType.fence, 321 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 322 srcData = Seq( 323 Seq(IntData(), IntData()), 324 ), 325 piped = true, 326 latency = CertainLatency(0), 327 exceptionOut = Seq(illegalInstr), 328 flushPipe = true 329 ) 330 331 // Todo: split it to simple bitmap exu and complex bku 332 val BkuCfg: FuConfig = FuConfig ( 333 name = "bku", 334 fuType = FuType.bku, 335 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 336 srcData = Seq( 337 Seq(IntData(), IntData()), 338 ), 339 piped = true, 340 writeIntRf = true, 341 latency = CertainLatency(2), 342 ) 343 344 val VSetRvfWvfCfg: FuConfig = FuConfig( 345 name = "vsetrvfwvf", 346 fuType = FuType.vsetfwf, 347 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 348 srcData = Seq( 349 Seq(FpData(), FpData()), 350 ), 351 piped = true, 352 writeVecRf = true, 353 writeVConfig = true, 354 latency = CertainLatency(0), 355 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 356 ) 357 358 val VSetRiWvfCfg: FuConfig = FuConfig( 359 name = "vsetriwvf", 360 fuType = FuType.vsetiwf, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 362 srcData = Seq( 363 Seq(IntData(), IntData()), 364 ), 365 piped = true, 366 writeVecRf = true, 367 writeVConfig = true, 368 latency = CertainLatency(0), 369 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 370 ) 371 372 val VSetRiWiCfg: FuConfig = FuConfig( 373 name = "vsetriwi", 374 fuType = FuType.vsetiwi, 375 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 376 srcData = Seq( 377 Seq(IntData(), IntData()), 378 ), 379 piped = true, 380 writeIntRf = true, 381 latency = CertainLatency(0), 382 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 383 ) 384 385 val FmacCfg: FuConfig = FuConfig ( 386 name = "fmac", 387 fuType = FuType.fmac, 388 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 389 srcData = Seq( 390 Seq(FpData(), FpData()), 391 Seq(FpData(), FpData(), FpData()), 392 ), 393 piped = false, 394 writeFpRf = true, 395 writeFflags = true, 396 latency = UncertainLatency(), 397 needSrcFrm = true, 398 ) 399 400 val F2iCfg: FuConfig = FuConfig ( 401 name = "f2i", 402 fuType = FuType.fmisc, 403 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 404 srcData = Seq( 405 Seq(FpData(), FpData()), 406 Seq(FpData()), 407 ), 408 piped = true, 409 writeIntRf = true, 410 writeFflags = true, 411 latency = CertainLatency(2), 412 needSrcFrm = true, 413 ) 414 415 val F2fCfg: FuConfig = FuConfig ( 416 name = "f2f", 417 fuType = FuType.fmisc, 418 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 419 srcData = Seq( 420 Seq(FpData(), FpData()), 421 Seq(FpData()), 422 ), 423 piped = true, 424 writeFpRf = true, 425 writeFflags = true, 426 latency = CertainLatency(2), 427 needSrcFrm = true, 428 ) 429 430 val FDivSqrtCfg: FuConfig = FuConfig ( 431 name = "fDivSqrt", 432 fuType = FuType.fDivSqrt, 433 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 434 srcData = Seq( 435 Seq(FpData(), FpData()), 436 ), 437 piped = false, 438 writeFpRf = true, 439 writeFflags = true, 440 latency = UncertainLatency(), 441 hasInputBuffer = (true, 8, true), 442 needSrcFrm = true, 443 ) 444 445 val LduCfg: FuConfig = FuConfig ( 446 name = "ldu", 447 fuType = FuType.ldu, 448 fuGen = null, // Todo 449 srcData = Seq( 450 Seq(IntData()), 451 ), 452 piped = false, // Todo: check it 453 writeIntRf = true, 454 writeFpRf = true, 455 latency = UncertainLatency(3), 456 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 457 flushPipe = true, 458 replayInst = true, 459 hasLoadError = true, 460 trigger = true, 461 immType = Set(SelImm.IMM_I), 462 ) 463 464 val StaCfg: FuConfig = FuConfig ( 465 name = "sta", 466 fuType = FuType.stu, 467 fuGen = null, // Todo 468 srcData = Seq( 469 Seq(IntData()), 470 ), 471 piped = false, 472 latency = UncertainLatency(), 473 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 474 trigger = true, 475 immType = Set(SelImm.IMM_S), 476 ) 477 478 val StdCfg: FuConfig = FuConfig ( 479 name = "std", 480 fuType = FuType.stu, 481 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 482 srcData = Seq( 483 Seq(IntData()), 484 Seq(FpData()), 485 ), 486 piped = true, 487 latency = CertainLatency(0) 488 ) 489 490 val HyldaCfg = FuConfig ( 491 name = "hylda", 492 fuType = FuType.ldu, 493 fuGen = null, // Todo 494 srcData = Seq( 495 Seq(IntData()), 496 ), 497 piped = false, // Todo: check it 498 writeIntRf = true, 499 writeFpRf = true, 500 latency = UncertainLatency(3), 501 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 502 flushPipe = true, 503 replayInst = true, 504 hasLoadError = true, 505 immType = Set(SelImm.IMM_I), 506 ) 507 508 val HystaCfg = FuConfig ( 509 name = "hysta", 510 fuType = FuType.stu, 511 fuGen = null, // Todo 512 srcData = Seq( 513 Seq(IntData()), 514 ), 515 piped = false, 516 latency = UncertainLatency(), 517 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 518 immType = Set(SelImm.IMM_S), 519 ) 520 521 val FakeHystaCfg = FuConfig ( 522 name = "hysta", 523 fuType = FuType.stu, 524 fuGen = null, // Todo 525 srcData = Seq(), 526 piped = false, 527 latency = UncertainLatency(), 528 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 529 immType = Set(), 530 ) 531 532 val MouCfg: FuConfig = FuConfig ( 533 name = "mou", 534 fuType = FuType.mou, 535 fuGen = null, // Todo 536 srcData = Seq( 537 Seq(IntData()), 538 ), 539 piped = false, // Todo: check it 540 writeFakeIntRf = true, 541 latency = UncertainLatency(), 542 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 543 trigger = true, 544 ) 545 546 val MoudCfg: FuConfig = FuConfig ( 547 name = "moud", 548 fuType = FuType.mou, 549 fuGen = null, // Todo 550 srcData = Seq( 551 Seq(IntData()), 552 ), 553 piped = true, 554 latency = CertainLatency(0), 555 ) 556 557 val VialuCfg = FuConfig ( 558 name = "vialuFix", 559 fuType = FuType.vialuF, 560 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 561 srcData = Seq( 562 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 563 ), 564 piped = true, 565 writeVecRf = true, 566 writeVxsat = true, 567 needSrcVxrm = true, 568 latency = CertainLatency(1), 569 vconfigWakeUp = true, 570 maskWakeUp = true, 571 dataBits = 128, 572 exceptionOut = Seq(illegalInstr), 573 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 574 ) 575 576 val VimacCfg = FuConfig ( 577 name = "vimac", 578 fuType = FuType.vimac, 579 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 580 srcData = Seq( 581 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 582 ), 583 piped = true, 584 writeVecRf = true, 585 writeVxsat = true, 586 needSrcVxrm = true, 587 latency = CertainLatency(2), 588 vconfigWakeUp = true, 589 maskWakeUp = true, 590 dataBits = 128, 591 exceptionOut = Seq(illegalInstr), 592 ) 593 594 val VidivCfg = FuConfig ( 595 name = "vidiv", 596 fuType = FuType.vidiv, 597 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 598 srcData = Seq( 599 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 600 ), 601 piped = false, 602 writeVecRf = true, 603 latency = UncertainLatency(), 604 vconfigWakeUp = true, 605 maskWakeUp = true, 606 dataBits = 128, 607 exceptionOut = Seq(illegalInstr), 608 ) 609 610 val VppuCfg = FuConfig ( 611 name = "vppu", 612 fuType = FuType.vppu, 613 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 614 srcData = Seq( 615 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 616 ), 617 piped = true, 618 writeVecRf = true, 619 latency = CertainLatency(2), 620 vconfigWakeUp = true, 621 maskWakeUp = true, 622 dataBits = 128, 623 exceptionOut = Seq(illegalInstr), 624 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 625 ) 626 627 val VipuCfg: FuConfig = FuConfig ( 628 name = "vipu", 629 fuType = FuType.vipu, 630 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 631 srcData = Seq( 632 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 633 ), 634 piped = true, 635 writeIntRf = true, 636 writeVecRf = true, 637 latency = CertainLatency(2), 638 vconfigWakeUp = true, 639 maskWakeUp = true, 640 dataBits = 128, 641 exceptionOut = Seq(illegalInstr), 642 ) 643 644 val VfaluCfg = FuConfig ( 645 name = "vfalu", 646 fuType = FuType.vfalu, 647 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 648 srcData = Seq( 649 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 650 ), 651 piped = true, 652 writeVecRf = true, 653 writeFpRf = true, 654 writeIntRf = true, 655 writeFflags = true, 656 latency = CertainLatency(1), 657 vconfigWakeUp = true, 658 maskWakeUp = true, 659 dataBits = 128, 660 exceptionOut = Seq(illegalInstr), 661 needSrcFrm = true, 662 ) 663 664 val VfmaCfg = FuConfig ( 665 name = "vfma", 666 fuType = FuType.vfma, 667 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 668 srcData = Seq( 669 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 670 ), 671 piped = true, 672 writeVecRf = true, 673 writeFpRf = true, 674 writeFflags = true, 675 latency = CertainLatency(3), 676 vconfigWakeUp = true, 677 maskWakeUp = true, 678 dataBits = 128, 679 exceptionOut = Seq(illegalInstr), 680 needSrcFrm = true, 681 ) 682 683 val VfdivCfg = FuConfig( 684 name = "vfdiv", 685 fuType = FuType.vfdiv, 686 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 687 srcData = Seq( 688 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 689 ), 690 piped = false, 691 writeVecRf = true, 692 writeFpRf = true, 693 writeFflags = true, 694 latency = UncertainLatency(), 695 vconfigWakeUp = true, 696 maskWakeUp = true, 697 dataBits = 128, 698 exceptionOut = Seq(illegalInstr), 699 needSrcFrm = true, 700 ) 701 702 val VfcvtCfg = FuConfig( 703 name = "vfcvt", 704 fuType = FuType.vfcvt, 705 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 706 srcData = Seq( 707 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 708 ), 709 piped = true, 710 writeVecRf = true, 711 writeFpRf = true, 712 writeIntRf = true, 713 writeFflags = true, 714 latency = CertainLatency(2), 715 vconfigWakeUp = true, 716 maskWakeUp = true, 717 dataBits = 128, 718 exceptionOut = Seq(illegalInstr), 719 needSrcFrm = true, 720 ) 721 722 723 val VlduCfg: FuConfig = FuConfig ( 724 name = "vldu", 725 fuType = FuType.vldu, 726 fuGen = null, 727 srcData = Seq( 728 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 729 ), 730 piped = false, // Todo: check it 731 writeVecRf = true, 732 latency = UncertainLatency(), 733 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 734 flushPipe = true, 735 replayInst = true, 736 hasLoadError = true, 737 vconfigWakeUp = true, 738 maskWakeUp = true, 739 dataBits = 128, 740 ) 741 742 val VstuCfg: FuConfig = FuConfig ( 743 name = "vstu", 744 fuType = FuType.vstu, 745 fuGen = null, 746 srcData = Seq( 747 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 748 ), 749 piped = false, 750 writeVecRf = false, 751 latency = UncertainLatency(), 752 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 753 flushPipe = true, 754 replayInst = true, 755 hasLoadError = true, 756 vconfigWakeUp = true, 757 maskWakeUp = true, 758 dataBits = 128, 759 ) 760 761 def allConfigs = Seq( 762 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 763 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 764 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 765 ) 766 767 def VecArithFuConfigs = Seq( 768 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 769 ) 770} 771 772