1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect also uses redirect bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def isVecMem: Boolean = fuType == FuType.vldu || fuType == FuType.vstu || 182 fuType == FuType.vsegldu || fuType == FuType.vsegstu 183 184 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || isVecMem 185 186 def isSta: Boolean = name.contains("sta") 187 188 def ckAlwaysEn: Boolean = isCsr || isFence 189 190 /** 191 * Get index of special src data, like [[VlData]], [[V0Data]] 192 * 193 * @param data [[DataConfig]] 194 * @param tips tips if get failed 195 * @return the index of special src data 196 */ 197 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 198 val srcIdxVec = srcData.map(x => x.indexOf(data)) 199 val idx0 = srcIdxVec.head 200 for (idx <- srcIdxVec) { 201 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 202 } 203 idx0 204 } 205 206 override def toString: String = { 207 var str = s"${this.name}: " 208 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 209 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 210 str += s"latency($latency)" 211 str += s"src($srcData)" 212 str 213 } 214} 215 216object FuConfig { 217 val JmpCfg: FuConfig = FuConfig ( 218 name = "jmp", 219 fuType = FuType.jmp, 220 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 221 srcData = Seq( 222 Seq(IntData()), // jal 223 ), 224 piped = true, 225 writeIntRf = true, 226 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 227 ) 228 229 val BrhCfg: FuConfig = FuConfig ( 230 name = "brh", 231 fuType = FuType.brh, 232 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 233 srcData = Seq( 234 Seq(IntData(), IntData()), 235 ), 236 piped = true, 237 immType = Set(SelImm.IMM_SB), 238 ) 239 240 val I2fCfg: FuConfig = FuConfig ( 241 name = "i2f", 242 FuType.i2f, 243 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 244 srcData = Seq( 245 Seq(IntData()), 246 ), 247 piped = true, 248 writeFpRf = true, 249 writeFflags = true, 250 latency = CertainLatency(2), 251 needSrcFrm = true, 252 ) 253 254 val I2vCfg: FuConfig = FuConfig ( 255 name = "i2v", 256 FuType.i2v, 257 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 258 srcData = Seq( 259 Seq(IntData(), IntData()), 260 ), 261 piped = true, 262 writeFpRf = true, 263 writeVecRf = true, 264 writeV0Rf = true, 265 latency = CertainLatency(0), 266 destDataBits = 128, 267 srcDataBits = Some(64), 268 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 269 ) 270 271 val F2vCfg: FuConfig = FuConfig ( 272 name = "f2v", 273 FuType.f2v, 274 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 275 srcData = Seq( 276 Seq(FpData(), FpData()), 277 Seq(FpData()), 278 ), 279 piped = true, 280 writeFpRf = true, 281 writeVecRf = true, 282 writeV0Rf = true, 283 latency = CertainLatency(0), 284 destDataBits = 128, 285 srcDataBits = Some(64), 286 ) 287 288 val CsrCfg: FuConfig = FuConfig ( 289 name = "csr", 290 fuType = FuType.csr, 291 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 292 srcData = Seq( 293 Seq(IntData()), 294 ), 295 piped = false, 296 writeIntRf = true, 297 latency = UncertainLatency(), 298 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 299 flushPipe = true, 300 ) 301 302 val AluCfg: FuConfig = FuConfig ( 303 name = "alu", 304 fuType = FuType.alu, 305 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 306 srcData = Seq( 307 Seq(IntData(), IntData()), 308 ), 309 piped = true, 310 writeIntRf = true, 311 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 312 ) 313 314 val MulCfg: FuConfig = FuConfig ( 315 name = "mul", 316 fuType = FuType.mul, 317 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 318 srcData = Seq( 319 Seq(IntData(), IntData()), 320 ), 321 piped = true, 322 writeIntRf = true, 323 latency = CertainLatency(2), 324 ) 325 326 val DivCfg: FuConfig = FuConfig ( 327 name = "div", 328 fuType = FuType.div, 329 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 330 srcData = Seq( 331 Seq(IntData(), IntData()), 332 ), 333 piped = false, 334 writeIntRf = true, 335 latency = UncertainLatency(), 336 hasInputBuffer = (true, 4, true) 337 ) 338 339 val FenceCfg: FuConfig = FuConfig ( 340 name = "fence", 341 FuType.fence, 342 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 343 srcData = Seq( 344 Seq(IntData(), IntData()), 345 ), 346 piped = false, 347 latency = UncertainLatency(), 348 exceptionOut = Seq(illegalInstr, virtualInstr), 349 flushPipe = true 350 ) 351 352 // Todo: split it to simple bitmap exu and complex bku 353 val BkuCfg: FuConfig = FuConfig ( 354 name = "bku", 355 fuType = FuType.bku, 356 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 357 srcData = Seq( 358 Seq(IntData(), IntData()), 359 ), 360 piped = true, 361 writeIntRf = true, 362 latency = CertainLatency(2), 363 ) 364 365 val VSetRvfWvfCfg: FuConfig = FuConfig( 366 name = "vsetrvfwvf", 367 fuType = FuType.vsetfwf, 368 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 369 srcData = Seq( 370 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 371 ), 372 piped = true, 373 writeVlRf = true, 374 writeVType = true, 375 writeIntRf = true, 376 latency = CertainLatency(0), 377 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 378 ) 379 380 val VSetRiWvfCfg: FuConfig = FuConfig( 381 name = "vsetriwvf", 382 fuType = FuType.vsetiwf, 383 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 384 srcData = Seq( 385 Seq(IntData(), IntData()), 386 ), 387 piped = true, 388 writeVlRf = true, 389 writeVType = true, 390 latency = CertainLatency(0), 391 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 392 ) 393 394 val VSetRiWiCfg: FuConfig = FuConfig( 395 name = "vsetriwi", 396 fuType = FuType.vsetiwi, 397 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 398 srcData = Seq( 399 Seq(IntData(), IntData()), 400 ), 401 piped = true, 402 writeIntRf = true, 403 latency = CertainLatency(0), 404 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 405 ) 406 407 val LduCfg: FuConfig = FuConfig ( 408 name = "ldu", 409 fuType = FuType.ldu, 410 fuGen = null, // Todo 411 srcData = Seq( 412 Seq(IntData()), 413 ), 414 piped = false, // Todo: check it 415 writeIntRf = true, 416 writeFpRf = true, 417 latency = UncertainLatency(3), 418 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault, breakPoint), 419 flushPipe = true, 420 replayInst = true, 421 hasLoadError = true, 422 trigger = true, 423 immType = Set(SelImm.IMM_I), 424 ) 425 426 val StaCfg: FuConfig = FuConfig ( 427 name = "sta", 428 fuType = FuType.stu, 429 fuGen = null, // Todo 430 srcData = Seq( 431 Seq(IntData()), 432 ), 433 piped = false, 434 latency = UncertainLatency(), 435 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault, breakPoint), 436 flushPipe = true, 437 trigger = true, 438 immType = Set(SelImm.IMM_S), 439 ) 440 441 val StdCfg: FuConfig = FuConfig ( 442 name = "std", 443 fuType = FuType.stu, 444 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 445 srcData = Seq( 446 Seq(IntData()), 447 Seq(FpData()), 448 ), 449 piped = true, 450 latency = CertainLatency(0) 451 ) 452 453 val HyldaCfg = FuConfig ( 454 name = "hylda", 455 fuType = FuType.ldu, 456 fuGen = null, // Todo 457 srcData = Seq( 458 Seq(IntData()), 459 ), 460 piped = false, // Todo: check it 461 writeIntRf = true, 462 writeFpRf = true, 463 latency = UncertainLatency(3), 464 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 465 flushPipe = true, 466 replayInst = true, 467 hasLoadError = true, 468 immType = Set(SelImm.IMM_I), 469 ) 470 471 val HystaCfg = FuConfig ( 472 name = "hysta", 473 fuType = FuType.stu, 474 fuGen = null, // Todo 475 srcData = Seq( 476 Seq(IntData()), 477 ), 478 piped = false, 479 latency = UncertainLatency(), 480 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 481 immType = Set(SelImm.IMM_S), 482 ) 483 484 val FakeHystaCfg = FuConfig ( 485 name = "hysta", 486 fuType = FuType.stu, 487 fuGen = null, // Todo 488 srcData = Seq(), 489 piped = false, 490 latency = UncertainLatency(), 491 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 492 immType = Set(), 493 ) 494 495 val MouCfg: FuConfig = FuConfig ( 496 name = "mou", 497 fuType = FuType.mou, 498 fuGen = null, // Todo 499 srcData = Seq( 500 Seq(IntData()), 501 ), 502 piped = false, // Todo: check it 503 writeFakeIntRf = true, 504 latency = UncertainLatency(), 505 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 506 trigger = true, 507 ) 508 509 val MoudCfg: FuConfig = FuConfig ( 510 name = "moud", 511 fuType = FuType.mou, 512 fuGen = null, // Todo 513 srcData = Seq( 514 Seq(IntData()), 515 ), 516 piped = true, 517 latency = CertainLatency(0), 518 ) 519 520 val VialuCfg = FuConfig ( 521 name = "vialuFix", 522 fuType = FuType.vialuF, 523 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 524 srcData = Seq( 525 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 526 ), 527 piped = true, 528 writeVecRf = true, 529 writeV0Rf = true, 530 writeVxsat = true, 531 needSrcVxrm = true, 532 latency = CertainLatency(1), 533 vconfigWakeUp = true, 534 maskWakeUp = true, 535 destDataBits = 128, 536 exceptionOut = Seq(illegalInstr), 537 ) 538 539 val VimacCfg = FuConfig ( 540 name = "vimac", 541 fuType = FuType.vimac, 542 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 543 srcData = Seq( 544 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 545 ), 546 piped = true, 547 writeVecRf = true, 548 writeV0Rf = true, 549 writeVxsat = true, 550 needSrcVxrm = true, 551 latency = CertainLatency(2), 552 vconfigWakeUp = true, 553 maskWakeUp = true, 554 destDataBits = 128, 555 exceptionOut = Seq(illegalInstr), 556 ) 557 558 val VidivCfg = FuConfig ( 559 name = "vidiv", 560 fuType = FuType.vidiv, 561 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 562 srcData = Seq( 563 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 564 ), 565 piped = false, 566 writeVecRf = true, 567 writeV0Rf = true, 568 latency = UncertainLatency(), 569 vconfigWakeUp = true, 570 maskWakeUp = true, 571 destDataBits = 128, 572 exceptionOut = Seq(illegalInstr), 573 ) 574 575 val VppuCfg = FuConfig ( 576 name = "vppu", 577 fuType = FuType.vppu, 578 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 579 srcData = Seq( 580 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 581 ), 582 piped = true, 583 writeVecRf = true, 584 writeV0Rf = true, 585 latency = CertainLatency(2), 586 vconfigWakeUp = true, 587 maskWakeUp = true, 588 destDataBits = 128, 589 exceptionOut = Seq(illegalInstr), 590 ) 591 592 val VipuCfg: FuConfig = FuConfig ( 593 name = "vipu", 594 fuType = FuType.vipu, 595 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 596 srcData = Seq( 597 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 598 ), 599 piped = true, 600 writeIntRf = true, 601 writeVecRf = true, 602 writeV0Rf = true, 603 latency = CertainLatency(2), 604 vconfigWakeUp = true, 605 maskWakeUp = true, 606 destDataBits = 128, 607 exceptionOut = Seq(illegalInstr), 608 ) 609 610 val VfaluCfg = FuConfig ( 611 name = "vfalu", 612 fuType = FuType.vfalu, 613 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 614 srcData = Seq( 615 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 616 ), 617 piped = true, 618 writeVecRf = true, 619 writeV0Rf = true, 620 writeFpRf = true, 621 writeFflags = true, 622 latency = CertainLatency(1), 623 vconfigWakeUp = true, 624 maskWakeUp = true, 625 destDataBits = 128, 626 exceptionOut = Seq(illegalInstr), 627 needSrcFrm = true, 628 ) 629 630 val VfmaCfg = FuConfig ( 631 name = "vfma", 632 fuType = FuType.vfma, 633 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 634 srcData = Seq( 635 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 636 ), 637 piped = true, 638 writeVecRf = true, 639 writeV0Rf = true, 640 writeFflags = true, 641 latency = CertainLatency(3), 642 vconfigWakeUp = true, 643 maskWakeUp = true, 644 destDataBits = 128, 645 exceptionOut = Seq(illegalInstr), 646 needSrcFrm = true, 647 ) 648 649 val VfdivCfg = FuConfig( 650 name = "vfdiv", 651 fuType = FuType.vfdiv, 652 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 653 srcData = Seq( 654 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 655 ), 656 piped = false, 657 writeVecRf = true, 658 writeV0Rf = true, 659 writeFflags = true, 660 latency = UncertainLatency(), 661 vconfigWakeUp = true, 662 maskWakeUp = true, 663 destDataBits = 128, 664 exceptionOut = Seq(illegalInstr), 665 needSrcFrm = true, 666 ) 667 668 val VfcvtCfg = FuConfig( 669 name = "vfcvt", 670 fuType = FuType.vfcvt, 671 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 672 srcData = Seq( 673 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 674 ), 675 piped = true, 676 writeVecRf = true, 677 writeV0Rf = true, 678 writeFflags = true, 679 latency = CertainLatency(2), 680 vconfigWakeUp = true, 681 maskWakeUp = true, 682 destDataBits = 128, 683 exceptionOut = Seq(illegalInstr), 684 needSrcFrm = true, 685 ) 686 687 val FaluCfg = FuConfig( 688 name = "falu", 689 fuType = FuType.falu, 690 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 691 srcData = Seq( 692 Seq(FpData(), FpData()), 693 ), 694 piped = true, 695 writeFpRf = true, 696 writeIntRf = true, 697 writeFflags = true, 698 latency = CertainLatency(1), 699 destDataBits = 64, 700 needSrcFrm = true, 701 ) 702 703 val FmacCfg = FuConfig( 704 name = "fmac", 705 fuType = FuType.fmac, 706 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 707 srcData = Seq( 708 Seq(FpData(), FpData(), FpData()), 709 ), 710 piped = true, 711 writeFpRf = true, 712 writeFflags = true, 713 latency = CertainLatency(3), 714 destDataBits = 64, 715 needSrcFrm = true, 716 ) 717 718 val FdivCfg = FuConfig( 719 name = "fdiv", 720 fuType = FuType.fDivSqrt, 721 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 722 srcData = Seq( 723 Seq(FpData(), FpData()), 724 ), 725 piped = false, 726 writeFpRf = true, 727 writeFflags = true, 728 latency = UncertainLatency(), 729 destDataBits = 64, 730 needSrcFrm = true, 731 ) 732 733 val FcvtCfg = FuConfig( 734 name = "fcvt", 735 fuType = FuType.fcvt, 736 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 737 srcData = Seq( 738 Seq(FpData()), 739 ), 740 piped = true, 741 writeFpRf = true, 742 writeIntRf = true, 743 writeFflags = true, 744 latency = CertainLatency(2), 745 destDataBits = 64, 746 needSrcFrm = true, 747 ) 748 749 val VlduCfg: FuConfig = FuConfig ( 750 name = "vldu", 751 fuType = FuType.vldu, 752 fuGen = null, 753 srcData = Seq( 754 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 755 ), 756 piped = false, // Todo: check it 757 writeVecRf = true, 758 writeV0Rf = true, 759 latency = UncertainLatency(), 760 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault, breakPoint), 761 flushPipe = true, 762 replayInst = true, 763 hasLoadError = true, 764 vconfigWakeUp = true, 765 maskWakeUp = true, 766 destDataBits = 128, 767 ) 768 769 val VstuCfg: FuConfig = FuConfig ( 770 name = "vstu", 771 fuType = FuType.vstu, 772 fuGen = null, 773 srcData = Seq( 774 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 775 ), 776 piped = false, 777 latency = UncertainLatency(), 778 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault, breakPoint), 779 flushPipe = true, 780 replayInst = true, 781 hasLoadError = true, 782 vconfigWakeUp = true, 783 maskWakeUp = true, 784 destDataBits = 128, 785 ) 786 787 val VseglduSeg: FuConfig = FuConfig ( 788 name = "vsegldu", 789 fuType = FuType.vsegldu, 790 fuGen = null, 791 srcData = Seq( 792 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 793 ), 794 piped = false, // Todo: check it 795 writeVecRf = true, 796 writeV0Rf = true, 797 latency = UncertainLatency(), 798 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, breakPoint), 799 flushPipe = true, 800 replayInst = true, 801 hasLoadError = true, 802 vconfigWakeUp = true, 803 maskWakeUp = true, 804 destDataBits = 128, 805 ) 806 807 val VsegstuCfg: FuConfig = FuConfig( 808 name = "vsegstu", 809 fuType = FuType.vsegstu, 810 fuGen = null, 811 srcData = Seq( 812 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 813 ), 814 piped = false, 815 latency = UncertainLatency(), 816 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, breakPoint), 817 flushPipe = true, 818 replayInst = true, 819 hasLoadError = true, 820 vconfigWakeUp = true, 821 maskWakeUp = true, 822 destDataBits = 128, 823 ) 824 825 def allConfigs = Seq( 826 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 827 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 828 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 829 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 830 ) 831 832 def VecArithFuConfigs = Seq( 833 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 834 ) 835} 836 837