1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect is in its exception bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf 182 183 def isSta: Boolean = name.contains("sta") 184 185 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 186 fuType == FuType.div || fuType == FuType.fDivSqrt || 187 fuType == FuType.vfdiv || fuType == FuType.vidiv 188 189 /** 190 * Get index of special src data, like [[VlData]], [[V0Data]] 191 * 192 * @param data [[DataConfig]] 193 * @param tips tips if get failed 194 * @return the index of special src data 195 */ 196 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 197 val srcIdxVec = srcData.map(x => x.indexOf(data)) 198 val idx0 = srcIdxVec.head 199 for (idx <- srcIdxVec) { 200 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 201 } 202 idx0 203 } 204 205 override def toString: String = { 206 var str = s"${this.name}: " 207 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 208 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 209 str += s"latency($latency)" 210 str += s"src($srcData)" 211 str 212 } 213} 214 215object FuConfig { 216 val JmpCfg: FuConfig = FuConfig ( 217 name = "jmp", 218 fuType = FuType.jmp, 219 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 220 srcData = Seq( 221 Seq(IntData()), // jal 222 ), 223 piped = true, 224 writeIntRf = true, 225 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 226 ) 227 228 val BrhCfg: FuConfig = FuConfig ( 229 name = "brh", 230 fuType = FuType.brh, 231 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 232 srcData = Seq( 233 Seq(IntData(), IntData()), 234 ), 235 piped = true, 236 immType = Set(SelImm.IMM_SB), 237 ) 238 239 val I2fCfg: FuConfig = FuConfig ( 240 name = "i2f", 241 FuType.i2f, 242 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 243 srcData = Seq( 244 Seq(IntData()), 245 ), 246 piped = true, 247 writeFpRf = true, 248 writeFflags = true, 249 latency = CertainLatency(2), 250 needSrcFrm = true, 251 ) 252 253 val I2vCfg: FuConfig = FuConfig ( 254 name = "i2v", 255 FuType.i2v, 256 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 257 srcData = Seq( 258 Seq(IntData(), IntData()), 259 ), 260 piped = true, 261 writeFpRf = true, 262 writeVecRf = true, 263 writeV0Rf = true, 264 latency = CertainLatency(0), 265 destDataBits = 128, 266 srcDataBits = Some(64), 267 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 268 ) 269 270 val F2vCfg: FuConfig = FuConfig ( 271 name = "f2v", 272 FuType.f2v, 273 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 274 srcData = Seq( 275 Seq(FpData(), FpData()), 276 Seq(FpData()), 277 ), 278 piped = true, 279 writeVecRf = true, 280 writeV0Rf = true, 281 latency = CertainLatency(0), 282 destDataBits = 128, 283 srcDataBits = Some(64), 284 ) 285 286 val CsrCfg: FuConfig = FuConfig ( 287 name = "csr", 288 fuType = FuType.csr, 289 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 290 srcData = Seq( 291 Seq(IntData()), 292 ), 293 piped = true, 294 writeIntRf = true, 295 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 296 flushPipe = true, 297 ) 298 299 val AluCfg: FuConfig = FuConfig ( 300 name = "alu", 301 fuType = FuType.alu, 302 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 303 srcData = Seq( 304 Seq(IntData(), IntData()), 305 ), 306 piped = true, 307 writeIntRf = true, 308 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 309 ) 310 311 val MulCfg: FuConfig = FuConfig ( 312 name = "mul", 313 fuType = FuType.mul, 314 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 315 srcData = Seq( 316 Seq(IntData(), IntData()), 317 ), 318 piped = true, 319 writeIntRf = true, 320 latency = CertainLatency(2), 321 ) 322 323 val DivCfg: FuConfig = FuConfig ( 324 name = "div", 325 fuType = FuType.div, 326 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 327 srcData = Seq( 328 Seq(IntData(), IntData()), 329 ), 330 piped = false, 331 writeIntRf = true, 332 latency = UncertainLatency(), 333 hasInputBuffer = (true, 4, true) 334 ) 335 336 val FenceCfg: FuConfig = FuConfig ( 337 name = "fence", 338 FuType.fence, 339 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 340 srcData = Seq( 341 Seq(IntData(), IntData()), 342 ), 343 piped = true, 344 latency = CertainLatency(0), 345 exceptionOut = Seq(illegalInstr, virtualInstr), 346 flushPipe = true 347 ) 348 349 // Todo: split it to simple bitmap exu and complex bku 350 val BkuCfg: FuConfig = FuConfig ( 351 name = "bku", 352 fuType = FuType.bku, 353 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 354 srcData = Seq( 355 Seq(IntData(), IntData()), 356 ), 357 piped = true, 358 writeIntRf = true, 359 latency = CertainLatency(2), 360 ) 361 362 val VSetRvfWvfCfg: FuConfig = FuConfig( 363 name = "vsetrvfwvf", 364 fuType = FuType.vsetfwf, 365 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 366 srcData = Seq( 367 Seq(VecData(), VecData()), 368 ), 369 piped = true, 370 writeVlRf = true, 371 writeVType = true, 372 latency = CertainLatency(0), 373 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 374 ) 375 376 val VSetRiWvfCfg: FuConfig = FuConfig( 377 name = "vsetriwvf", 378 fuType = FuType.vsetiwf, 379 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 380 srcData = Seq( 381 Seq(IntData(), IntData()), 382 ), 383 piped = true, 384 writeVlRf = true, 385 writeVType = true, 386 latency = CertainLatency(0), 387 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 388 ) 389 390 val VSetRiWiCfg: FuConfig = FuConfig( 391 name = "vsetriwi", 392 fuType = FuType.vsetiwi, 393 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 394 srcData = Seq( 395 Seq(IntData(), IntData()), 396 ), 397 piped = true, 398 writeIntRf = true, 399 latency = CertainLatency(0), 400 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 401 ) 402 403 val LduCfg: FuConfig = FuConfig ( 404 name = "ldu", 405 fuType = FuType.ldu, 406 fuGen = null, // Todo 407 srcData = Seq( 408 Seq(IntData()), 409 ), 410 piped = false, // Todo: check it 411 writeIntRf = true, 412 writeFpRf = true, 413 latency = UncertainLatency(3), 414 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 415 flushPipe = true, 416 replayInst = true, 417 hasLoadError = true, 418 trigger = true, 419 immType = Set(SelImm.IMM_I), 420 ) 421 422 val StaCfg: FuConfig = FuConfig ( 423 name = "sta", 424 fuType = FuType.stu, 425 fuGen = null, // Todo 426 srcData = Seq( 427 Seq(IntData()), 428 ), 429 piped = false, 430 latency = UncertainLatency(), 431 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 432 trigger = true, 433 immType = Set(SelImm.IMM_S), 434 ) 435 436 val StdCfg: FuConfig = FuConfig ( 437 name = "std", 438 fuType = FuType.stu, 439 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 440 srcData = Seq( 441 Seq(IntData()), 442 Seq(FpData()), 443 ), 444 piped = true, 445 latency = CertainLatency(0) 446 ) 447 448 val HyldaCfg = FuConfig ( 449 name = "hylda", 450 fuType = FuType.ldu, 451 fuGen = null, // Todo 452 srcData = Seq( 453 Seq(IntData()), 454 ), 455 piped = false, // Todo: check it 456 writeIntRf = true, 457 writeFpRf = true, 458 latency = UncertainLatency(3), 459 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 460 flushPipe = true, 461 replayInst = true, 462 hasLoadError = true, 463 immType = Set(SelImm.IMM_I), 464 ) 465 466 val HystaCfg = FuConfig ( 467 name = "hysta", 468 fuType = FuType.stu, 469 fuGen = null, // Todo 470 srcData = Seq( 471 Seq(IntData()), 472 ), 473 piped = false, 474 latency = UncertainLatency(), 475 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 476 immType = Set(SelImm.IMM_S), 477 ) 478 479 val FakeHystaCfg = FuConfig ( 480 name = "hysta", 481 fuType = FuType.stu, 482 fuGen = null, // Todo 483 srcData = Seq(), 484 piped = false, 485 latency = UncertainLatency(), 486 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 487 immType = Set(), 488 ) 489 490 val MouCfg: FuConfig = FuConfig ( 491 name = "mou", 492 fuType = FuType.mou, 493 fuGen = null, // Todo 494 srcData = Seq( 495 Seq(IntData()), 496 ), 497 piped = false, // Todo: check it 498 writeFakeIntRf = true, 499 latency = UncertainLatency(), 500 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 501 trigger = true, 502 ) 503 504 val MoudCfg: FuConfig = FuConfig ( 505 name = "moud", 506 fuType = FuType.mou, 507 fuGen = null, // Todo 508 srcData = Seq( 509 Seq(IntData()), 510 ), 511 piped = true, 512 latency = CertainLatency(0), 513 ) 514 515 val VialuCfg = FuConfig ( 516 name = "vialuFix", 517 fuType = FuType.vialuF, 518 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 519 srcData = Seq( 520 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 521 ), 522 piped = true, 523 writeVecRf = true, 524 writeV0Rf = true, 525 writeVxsat = true, 526 needSrcVxrm = true, 527 latency = CertainLatency(1), 528 vconfigWakeUp = true, 529 maskWakeUp = true, 530 destDataBits = 128, 531 exceptionOut = Seq(illegalInstr), 532 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 533 ) 534 535 val VimacCfg = FuConfig ( 536 name = "vimac", 537 fuType = FuType.vimac, 538 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 539 srcData = Seq( 540 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 541 ), 542 piped = true, 543 writeVecRf = true, 544 writeV0Rf = true, 545 writeVxsat = true, 546 needSrcVxrm = true, 547 latency = CertainLatency(2), 548 vconfigWakeUp = true, 549 maskWakeUp = true, 550 destDataBits = 128, 551 exceptionOut = Seq(illegalInstr), 552 ) 553 554 val VidivCfg = FuConfig ( 555 name = "vidiv", 556 fuType = FuType.vidiv, 557 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 558 srcData = Seq( 559 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 560 ), 561 piped = false, 562 writeVecRf = true, 563 writeV0Rf = true, 564 latency = UncertainLatency(), 565 vconfigWakeUp = true, 566 maskWakeUp = true, 567 destDataBits = 128, 568 exceptionOut = Seq(illegalInstr), 569 ) 570 571 val VppuCfg = FuConfig ( 572 name = "vppu", 573 fuType = FuType.vppu, 574 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 575 srcData = Seq( 576 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 577 ), 578 piped = true, 579 writeVecRf = true, 580 writeV0Rf = true, 581 latency = CertainLatency(2), 582 vconfigWakeUp = true, 583 maskWakeUp = true, 584 destDataBits = 128, 585 exceptionOut = Seq(illegalInstr), 586 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 587 ) 588 589 val VipuCfg: FuConfig = FuConfig ( 590 name = "vipu", 591 fuType = FuType.vipu, 592 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 593 srcData = Seq( 594 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 595 ), 596 piped = true, 597 writeIntRf = true, 598 writeVecRf = true, 599 writeV0Rf = true, 600 latency = CertainLatency(2), 601 vconfigWakeUp = true, 602 maskWakeUp = true, 603 destDataBits = 128, 604 exceptionOut = Seq(illegalInstr), 605 ) 606 607 val VfaluCfg = FuConfig ( 608 name = "vfalu", 609 fuType = FuType.vfalu, 610 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 611 srcData = Seq( 612 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 613 ), 614 piped = true, 615 writeVecRf = true, 616 writeV0Rf = true, 617 writeFpRf = true, 618 writeFflags = true, 619 latency = CertainLatency(1), 620 vconfigWakeUp = true, 621 maskWakeUp = true, 622 destDataBits = 128, 623 exceptionOut = Seq(illegalInstr), 624 needSrcFrm = true, 625 ) 626 627 val VfmaCfg = FuConfig ( 628 name = "vfma", 629 fuType = FuType.vfma, 630 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 631 srcData = Seq( 632 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 633 ), 634 piped = true, 635 writeVecRf = true, 636 writeV0Rf = true, 637 writeFflags = true, 638 latency = CertainLatency(3), 639 vconfigWakeUp = true, 640 maskWakeUp = true, 641 destDataBits = 128, 642 exceptionOut = Seq(illegalInstr), 643 needSrcFrm = true, 644 ) 645 646 val VfdivCfg = FuConfig( 647 name = "vfdiv", 648 fuType = FuType.vfdiv, 649 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 650 srcData = Seq( 651 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 652 ), 653 piped = false, 654 writeVecRf = true, 655 writeV0Rf = true, 656 writeFflags = true, 657 latency = UncertainLatency(), 658 vconfigWakeUp = true, 659 maskWakeUp = true, 660 destDataBits = 128, 661 exceptionOut = Seq(illegalInstr), 662 needSrcFrm = true, 663 ) 664 665 val VfcvtCfg = FuConfig( 666 name = "vfcvt", 667 fuType = FuType.vfcvt, 668 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 669 srcData = Seq( 670 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 671 ), 672 piped = true, 673 writeVecRf = true, 674 writeV0Rf = true, 675 writeFflags = true, 676 latency = CertainLatency(2), 677 vconfigWakeUp = true, 678 maskWakeUp = true, 679 destDataBits = 128, 680 exceptionOut = Seq(illegalInstr), 681 needSrcFrm = true, 682 ) 683 684 val FaluCfg = FuConfig( 685 name = "falu", 686 fuType = FuType.falu, 687 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 688 srcData = Seq( 689 Seq(FpData(), FpData()), 690 ), 691 piped = true, 692 writeFpRf = true, 693 writeIntRf = true, 694 writeFflags = true, 695 latency = CertainLatency(1), 696 destDataBits = 64, 697 needSrcFrm = true, 698 ) 699 700 val FmacCfg = FuConfig( 701 name = "fmac", 702 fuType = FuType.fmac, 703 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 704 srcData = Seq( 705 Seq(FpData(), FpData(), FpData()), 706 ), 707 piped = true, 708 writeFpRf = true, 709 writeFflags = true, 710 latency = CertainLatency(3), 711 destDataBits = 64, 712 needSrcFrm = true, 713 ) 714 715 val FdivCfg = FuConfig( 716 name = "fdiv", 717 fuType = FuType.fDivSqrt, 718 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 719 srcData = Seq( 720 Seq(FpData(), FpData()), 721 ), 722 piped = false, 723 writeFpRf = true, 724 writeFflags = true, 725 latency = UncertainLatency(), 726 destDataBits = 64, 727 needSrcFrm = true, 728 ) 729 730 val FcvtCfg = FuConfig( 731 name = "fcvt", 732 fuType = FuType.fcvt, 733 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 734 srcData = Seq( 735 Seq(FpData()), 736 ), 737 piped = true, 738 writeFpRf = true, 739 writeIntRf = true, 740 writeFflags = true, 741 latency = CertainLatency(2), 742 destDataBits = 64, 743 needSrcFrm = true, 744 ) 745 746 val VlduCfg: FuConfig = FuConfig ( 747 name = "vldu", 748 fuType = FuType.vldu, 749 fuGen = null, 750 srcData = Seq( 751 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 752 ), 753 piped = false, // Todo: check it 754 writeVecRf = true, 755 writeV0Rf = true, 756 latency = UncertainLatency(), 757 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 758 flushPipe = true, 759 replayInst = true, 760 hasLoadError = true, 761 vconfigWakeUp = true, 762 maskWakeUp = true, 763 destDataBits = 128, 764 ) 765 766 val VstuCfg: FuConfig = FuConfig ( 767 name = "vstu", 768 fuType = FuType.vstu, 769 fuGen = null, 770 srcData = Seq( 771 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 772 ), 773 piped = false, 774 latency = UncertainLatency(), 775 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 776 flushPipe = true, 777 replayInst = true, 778 hasLoadError = true, 779 vconfigWakeUp = true, 780 maskWakeUp = true, 781 destDataBits = 128, 782 ) 783 784 val VseglduSeg: FuConfig = FuConfig ( 785 name = "vsegldu", 786 fuType = FuType.vsegldu, 787 fuGen = null, 788 srcData = Seq( 789 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 790 ), 791 piped = false, // Todo: check it 792 writeVecRf = true, 793 writeV0Rf = true, 794 latency = UncertainLatency(), 795 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 796 flushPipe = true, 797 replayInst = true, 798 hasLoadError = true, 799 vconfigWakeUp = true, 800 maskWakeUp = true, 801 destDataBits = 128, 802 ) 803 804 val VsegstuCfg: FuConfig = FuConfig( 805 name = "vsegstu", 806 fuType = FuType.vsegstu, 807 fuGen = null, 808 srcData = Seq( 809 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 810 ), 811 piped = false, 812 latency = UncertainLatency(), 813 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 814 flushPipe = true, 815 replayInst = true, 816 hasLoadError = true, 817 vconfigWakeUp = true, 818 maskWakeUp = true, 819 destDataBits = 128, 820 ) 821 822 def allConfigs = Seq( 823 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 824 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 825 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 826 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 827 ) 828 829 def VecArithFuConfigs = Seq( 830 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 831 ) 832} 833 834