1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect also uses redirect bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf 182 183 def isSta: Boolean = name.contains("sta") 184 185 def ckAlwaysEn: Boolean = isCsr || isFence 186 187 /** 188 * Get index of special src data, like [[VlData]], [[V0Data]] 189 * 190 * @param data [[DataConfig]] 191 * @param tips tips if get failed 192 * @return the index of special src data 193 */ 194 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 195 val srcIdxVec = srcData.map(x => x.indexOf(data)) 196 val idx0 = srcIdxVec.head 197 for (idx <- srcIdxVec) { 198 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 199 } 200 idx0 201 } 202 203 override def toString: String = { 204 var str = s"${this.name}: " 205 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 206 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 207 str += s"latency($latency)" 208 str += s"src($srcData)" 209 str 210 } 211} 212 213object FuConfig { 214 val JmpCfg: FuConfig = FuConfig ( 215 name = "jmp", 216 fuType = FuType.jmp, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 218 srcData = Seq( 219 Seq(IntData()), // jal 220 ), 221 piped = true, 222 writeIntRf = true, 223 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 224 ) 225 226 val BrhCfg: FuConfig = FuConfig ( 227 name = "brh", 228 fuType = FuType.brh, 229 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 230 srcData = Seq( 231 Seq(IntData(), IntData()), 232 ), 233 piped = true, 234 immType = Set(SelImm.IMM_SB), 235 ) 236 237 val I2fCfg: FuConfig = FuConfig ( 238 name = "i2f", 239 FuType.i2f, 240 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 241 srcData = Seq( 242 Seq(IntData()), 243 ), 244 piped = true, 245 writeFpRf = true, 246 writeFflags = true, 247 latency = CertainLatency(2), 248 needSrcFrm = true, 249 ) 250 251 val I2vCfg: FuConfig = FuConfig ( 252 name = "i2v", 253 FuType.i2v, 254 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 255 srcData = Seq( 256 Seq(IntData(), IntData()), 257 ), 258 piped = true, 259 writeFpRf = true, 260 writeVecRf = true, 261 writeV0Rf = true, 262 latency = CertainLatency(0), 263 destDataBits = 128, 264 srcDataBits = Some(64), 265 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 266 ) 267 268 val F2vCfg: FuConfig = FuConfig ( 269 name = "f2v", 270 FuType.f2v, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 272 srcData = Seq( 273 Seq(FpData(), FpData()), 274 Seq(FpData()), 275 ), 276 piped = true, 277 writeVecRf = true, 278 writeV0Rf = true, 279 latency = CertainLatency(0), 280 destDataBits = 128, 281 srcDataBits = Some(64), 282 ) 283 284 val CsrCfg: FuConfig = FuConfig ( 285 name = "csr", 286 fuType = FuType.csr, 287 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 288 srcData = Seq( 289 Seq(IntData()), 290 ), 291 piped = false, 292 writeIntRf = true, 293 latency = UncertainLatency(), 294 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 295 flushPipe = true, 296 ) 297 298 val AluCfg: FuConfig = FuConfig ( 299 name = "alu", 300 fuType = FuType.alu, 301 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 302 srcData = Seq( 303 Seq(IntData(), IntData()), 304 ), 305 piped = true, 306 writeIntRf = true, 307 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 308 ) 309 310 val MulCfg: FuConfig = FuConfig ( 311 name = "mul", 312 fuType = FuType.mul, 313 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 314 srcData = Seq( 315 Seq(IntData(), IntData()), 316 ), 317 piped = true, 318 writeIntRf = true, 319 latency = CertainLatency(2), 320 ) 321 322 val DivCfg: FuConfig = FuConfig ( 323 name = "div", 324 fuType = FuType.div, 325 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 326 srcData = Seq( 327 Seq(IntData(), IntData()), 328 ), 329 piped = false, 330 writeIntRf = true, 331 latency = UncertainLatency(), 332 hasInputBuffer = (true, 4, true) 333 ) 334 335 val FenceCfg: FuConfig = FuConfig ( 336 name = "fence", 337 FuType.fence, 338 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 339 srcData = Seq( 340 Seq(IntData(), IntData()), 341 ), 342 piped = false, 343 latency = UncertainLatency(), 344 exceptionOut = Seq(illegalInstr, virtualInstr), 345 flushPipe = true 346 ) 347 348 // Todo: split it to simple bitmap exu and complex bku 349 val BkuCfg: FuConfig = FuConfig ( 350 name = "bku", 351 fuType = FuType.bku, 352 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 353 srcData = Seq( 354 Seq(IntData(), IntData()), 355 ), 356 piped = true, 357 writeIntRf = true, 358 latency = CertainLatency(2), 359 ) 360 361 val VSetRvfWvfCfg: FuConfig = FuConfig( 362 name = "vsetrvfwvf", 363 fuType = FuType.vsetfwf, 364 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 365 srcData = Seq( 366 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 367 ), 368 piped = true, 369 writeVlRf = true, 370 writeVType = true, 371 writeIntRf = true, 372 latency = CertainLatency(0), 373 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 374 ) 375 376 val VSetRiWvfCfg: FuConfig = FuConfig( 377 name = "vsetriwvf", 378 fuType = FuType.vsetiwf, 379 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 380 srcData = Seq( 381 Seq(IntData(), IntData()), 382 ), 383 piped = true, 384 writeVlRf = true, 385 writeVType = true, 386 latency = CertainLatency(0), 387 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 388 ) 389 390 val VSetRiWiCfg: FuConfig = FuConfig( 391 name = "vsetriwi", 392 fuType = FuType.vsetiwi, 393 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 394 srcData = Seq( 395 Seq(IntData(), IntData()), 396 ), 397 piped = true, 398 writeIntRf = true, 399 latency = CertainLatency(0), 400 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 401 ) 402 403 val LduCfg: FuConfig = FuConfig ( 404 name = "ldu", 405 fuType = FuType.ldu, 406 fuGen = null, // Todo 407 srcData = Seq( 408 Seq(IntData()), 409 ), 410 piped = false, // Todo: check it 411 writeIntRf = true, 412 writeFpRf = true, 413 latency = UncertainLatency(3), 414 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 415 flushPipe = true, 416 replayInst = true, 417 hasLoadError = true, 418 trigger = true, 419 immType = Set(SelImm.IMM_I), 420 ) 421 422 val StaCfg: FuConfig = FuConfig ( 423 name = "sta", 424 fuType = FuType.stu, 425 fuGen = null, // Todo 426 srcData = Seq( 427 Seq(IntData()), 428 ), 429 piped = false, 430 latency = UncertainLatency(), 431 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault, breakPoint), 432 trigger = true, 433 immType = Set(SelImm.IMM_S), 434 ) 435 436 val StdCfg: FuConfig = FuConfig ( 437 name = "std", 438 fuType = FuType.stu, 439 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 440 srcData = Seq( 441 Seq(IntData()), 442 Seq(FpData()), 443 ), 444 piped = true, 445 latency = CertainLatency(0) 446 ) 447 448 val HyldaCfg = FuConfig ( 449 name = "hylda", 450 fuType = FuType.ldu, 451 fuGen = null, // Todo 452 srcData = Seq( 453 Seq(IntData()), 454 ), 455 piped = false, // Todo: check it 456 writeIntRf = true, 457 writeFpRf = true, 458 latency = UncertainLatency(3), 459 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 460 flushPipe = true, 461 replayInst = true, 462 hasLoadError = true, 463 immType = Set(SelImm.IMM_I), 464 ) 465 466 val HystaCfg = FuConfig ( 467 name = "hysta", 468 fuType = FuType.stu, 469 fuGen = null, // Todo 470 srcData = Seq( 471 Seq(IntData()), 472 ), 473 piped = false, 474 latency = UncertainLatency(), 475 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 476 immType = Set(SelImm.IMM_S), 477 ) 478 479 val FakeHystaCfg = FuConfig ( 480 name = "hysta", 481 fuType = FuType.stu, 482 fuGen = null, // Todo 483 srcData = Seq(), 484 piped = false, 485 latency = UncertainLatency(), 486 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 487 immType = Set(), 488 ) 489 490 val MouCfg: FuConfig = FuConfig ( 491 name = "mou", 492 fuType = FuType.mou, 493 fuGen = null, // Todo 494 srcData = Seq( 495 Seq(IntData()), 496 ), 497 piped = false, // Todo: check it 498 writeFakeIntRf = true, 499 latency = UncertainLatency(), 500 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 501 trigger = true, 502 ) 503 504 val MoudCfg: FuConfig = FuConfig ( 505 name = "moud", 506 fuType = FuType.mou, 507 fuGen = null, // Todo 508 srcData = Seq( 509 Seq(IntData()), 510 ), 511 piped = true, 512 latency = CertainLatency(0), 513 ) 514 515 val VialuCfg = FuConfig ( 516 name = "vialuFix", 517 fuType = FuType.vialuF, 518 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 519 srcData = Seq( 520 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 521 ), 522 piped = true, 523 writeVecRf = true, 524 writeV0Rf = true, 525 writeVxsat = true, 526 needSrcVxrm = true, 527 latency = CertainLatency(1), 528 vconfigWakeUp = true, 529 maskWakeUp = true, 530 destDataBits = 128, 531 exceptionOut = Seq(illegalInstr), 532 ) 533 534 val VimacCfg = FuConfig ( 535 name = "vimac", 536 fuType = FuType.vimac, 537 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 538 srcData = Seq( 539 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 540 ), 541 piped = true, 542 writeVecRf = true, 543 writeV0Rf = true, 544 writeVxsat = true, 545 needSrcVxrm = true, 546 latency = CertainLatency(2), 547 vconfigWakeUp = true, 548 maskWakeUp = true, 549 destDataBits = 128, 550 exceptionOut = Seq(illegalInstr), 551 ) 552 553 val VidivCfg = FuConfig ( 554 name = "vidiv", 555 fuType = FuType.vidiv, 556 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 557 srcData = Seq( 558 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 559 ), 560 piped = false, 561 writeVecRf = true, 562 writeV0Rf = true, 563 latency = UncertainLatency(), 564 vconfigWakeUp = true, 565 maskWakeUp = true, 566 destDataBits = 128, 567 exceptionOut = Seq(illegalInstr), 568 ) 569 570 val VppuCfg = FuConfig ( 571 name = "vppu", 572 fuType = FuType.vppu, 573 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 574 srcData = Seq( 575 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 576 ), 577 piped = true, 578 writeVecRf = true, 579 writeV0Rf = true, 580 latency = CertainLatency(2), 581 vconfigWakeUp = true, 582 maskWakeUp = true, 583 destDataBits = 128, 584 exceptionOut = Seq(illegalInstr), 585 ) 586 587 val VipuCfg: FuConfig = FuConfig ( 588 name = "vipu", 589 fuType = FuType.vipu, 590 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 591 srcData = Seq( 592 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 593 ), 594 piped = true, 595 writeIntRf = true, 596 writeVecRf = true, 597 writeV0Rf = true, 598 latency = CertainLatency(2), 599 vconfigWakeUp = true, 600 maskWakeUp = true, 601 destDataBits = 128, 602 exceptionOut = Seq(illegalInstr), 603 ) 604 605 val VfaluCfg = FuConfig ( 606 name = "vfalu", 607 fuType = FuType.vfalu, 608 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 609 srcData = Seq( 610 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 611 ), 612 piped = true, 613 writeVecRf = true, 614 writeV0Rf = true, 615 writeFpRf = true, 616 writeFflags = true, 617 latency = CertainLatency(1), 618 vconfigWakeUp = true, 619 maskWakeUp = true, 620 destDataBits = 128, 621 exceptionOut = Seq(illegalInstr), 622 needSrcFrm = true, 623 ) 624 625 val VfmaCfg = FuConfig ( 626 name = "vfma", 627 fuType = FuType.vfma, 628 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 629 srcData = Seq( 630 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 631 ), 632 piped = true, 633 writeVecRf = true, 634 writeV0Rf = true, 635 writeFflags = true, 636 latency = CertainLatency(3), 637 vconfigWakeUp = true, 638 maskWakeUp = true, 639 destDataBits = 128, 640 exceptionOut = Seq(illegalInstr), 641 needSrcFrm = true, 642 ) 643 644 val VfdivCfg = FuConfig( 645 name = "vfdiv", 646 fuType = FuType.vfdiv, 647 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 648 srcData = Seq( 649 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 650 ), 651 piped = false, 652 writeVecRf = true, 653 writeV0Rf = true, 654 writeFflags = true, 655 latency = UncertainLatency(), 656 vconfigWakeUp = true, 657 maskWakeUp = true, 658 destDataBits = 128, 659 exceptionOut = Seq(illegalInstr), 660 needSrcFrm = true, 661 ) 662 663 val VfcvtCfg = FuConfig( 664 name = "vfcvt", 665 fuType = FuType.vfcvt, 666 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 667 srcData = Seq( 668 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 669 ), 670 piped = true, 671 writeVecRf = true, 672 writeV0Rf = true, 673 writeFflags = true, 674 latency = CertainLatency(2), 675 vconfigWakeUp = true, 676 maskWakeUp = true, 677 destDataBits = 128, 678 exceptionOut = Seq(illegalInstr), 679 needSrcFrm = true, 680 ) 681 682 val FaluCfg = FuConfig( 683 name = "falu", 684 fuType = FuType.falu, 685 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 686 srcData = Seq( 687 Seq(FpData(), FpData()), 688 ), 689 piped = true, 690 writeFpRf = true, 691 writeIntRf = true, 692 writeFflags = true, 693 latency = CertainLatency(1), 694 destDataBits = 64, 695 needSrcFrm = true, 696 ) 697 698 val FmacCfg = FuConfig( 699 name = "fmac", 700 fuType = FuType.fmac, 701 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 702 srcData = Seq( 703 Seq(FpData(), FpData(), FpData()), 704 ), 705 piped = true, 706 writeFpRf = true, 707 writeFflags = true, 708 latency = CertainLatency(3), 709 destDataBits = 64, 710 needSrcFrm = true, 711 ) 712 713 val FdivCfg = FuConfig( 714 name = "fdiv", 715 fuType = FuType.fDivSqrt, 716 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 717 srcData = Seq( 718 Seq(FpData(), FpData()), 719 ), 720 piped = false, 721 writeFpRf = true, 722 writeFflags = true, 723 latency = UncertainLatency(), 724 destDataBits = 64, 725 needSrcFrm = true, 726 ) 727 728 val FcvtCfg = FuConfig( 729 name = "fcvt", 730 fuType = FuType.fcvt, 731 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 732 srcData = Seq( 733 Seq(FpData()), 734 ), 735 piped = true, 736 writeFpRf = true, 737 writeIntRf = true, 738 writeFflags = true, 739 latency = CertainLatency(2), 740 destDataBits = 64, 741 needSrcFrm = true, 742 ) 743 744 val VlduCfg: FuConfig = FuConfig ( 745 name = "vldu", 746 fuType = FuType.vldu, 747 fuGen = null, 748 srcData = Seq( 749 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 750 ), 751 piped = false, // Todo: check it 752 writeVecRf = true, 753 writeV0Rf = true, 754 latency = UncertainLatency(), 755 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 756 flushPipe = true, 757 replayInst = true, 758 hasLoadError = true, 759 vconfigWakeUp = true, 760 maskWakeUp = true, 761 destDataBits = 128, 762 ) 763 764 val VstuCfg: FuConfig = FuConfig ( 765 name = "vstu", 766 fuType = FuType.vstu, 767 fuGen = null, 768 srcData = Seq( 769 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 770 ), 771 piped = false, 772 latency = UncertainLatency(), 773 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 774 flushPipe = true, 775 replayInst = true, 776 hasLoadError = true, 777 vconfigWakeUp = true, 778 maskWakeUp = true, 779 destDataBits = 128, 780 ) 781 782 val VseglduSeg: FuConfig = FuConfig ( 783 name = "vsegldu", 784 fuType = FuType.vsegldu, 785 fuGen = null, 786 srcData = Seq( 787 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 788 ), 789 piped = false, // Todo: check it 790 writeVecRf = true, 791 writeV0Rf = true, 792 latency = UncertainLatency(), 793 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 794 flushPipe = true, 795 replayInst = true, 796 hasLoadError = true, 797 vconfigWakeUp = true, 798 maskWakeUp = true, 799 destDataBits = 128, 800 ) 801 802 val VsegstuCfg: FuConfig = FuConfig( 803 name = "vsegstu", 804 fuType = FuType.vsegstu, 805 fuGen = null, 806 srcData = Seq( 807 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 808 ), 809 piped = false, 810 latency = UncertainLatency(), 811 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 812 flushPipe = true, 813 replayInst = true, 814 hasLoadError = true, 815 vconfigWakeUp = true, 816 maskWakeUp = true, 817 destDataBits = 128, 818 ) 819 820 def allConfigs = Seq( 821 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 822 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 823 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 824 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 825 ) 826 827 def VecArithFuConfigs = Seq( 828 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 829 ) 830} 831 832