1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeV0Rf : Boolean = false, 54 writeVlRf : Boolean = false, 55 writeFakeIntRf: Boolean = false, 56 writeFflags : Boolean = false, 57 writeVxsat : Boolean = false, 58 dataBits : Int = 64, 59 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 60 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 61 exceptionOut : Seq[Int] = Seq(), 62 hasLoadError : Boolean = false, 63 flushPipe : Boolean = false, 64 replayInst : Boolean = false, 65 trigger : Boolean = false, 66 needSrcFrm : Boolean = false, 67 needSrcVxrm : Boolean = false, 68 writeVConfig : Boolean = false, 69 writeVType : Boolean = false, 70 immType : Set[UInt] = Set(), 71 // vector 72 vconfigWakeUp : Boolean = false, 73 maskWakeUp : Boolean = false, 74) { 75 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 76 def needFpWen: Boolean = writeFpRf 77 def needVecWen: Boolean = writeVecRf 78 var vconfigIdx = -1 79 var maskSrcIdx = -1 80 if (vconfigWakeUp) { 81 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 82 } 83 if (maskWakeUp) { 84 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 85 } 86 87 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 88 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 89 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 90 91 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 93 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 94 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 95 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 96 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 97 98 def readFp: Boolean = numFpSrc > 0 99 100 def fuSel(uop: ExuInput): Bool = { 101 // Don't add more shit here!!! 102 // Todo: add new FuType to distinguish f2i, f2f 103 uop.fuType === this.fuType.U 104 } 105 106 /** 107 * params(i): data type set of the ith src port 108 * @return 109 */ 110 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 111 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 112 // make srcData is uniform sized to avoid exception when transpose 113 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 114 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 115 } 116 117 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 118 srcData 119 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 120 .filter(_.nonEmpty) 121 .map(_.get) 122 .toSet 123 } 124 125 def hasNoDataWB: Boolean = { 126 !(writeIntRf || writeFpRf || writeVecRf) 127 } 128 129 def getSrcMaxWidthVec = { 130 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 131 } 132 133 def genSrcDataVec: Seq[UInt] = { 134 getSrcMaxWidthVec.map(w => UInt(w.W)) 135 } 136 137 // csr's redirect is in its exception bundle 138 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 139 140 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 141 142 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 // predict info 145 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 146 147 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 148 149 def needFPUCtrl: Boolean = { 150 import FuType._ 151 Seq(fmac, fDivSqrt, i2f).contains(fuType) 152 } 153 154 def needVecCtrl: Boolean = { 155 import FuType._ 156 Seq(falu, fmac, fDivSqrt, fcvt, 157 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 158 } 159 160 def isMul: Boolean = fuType == FuType.mul 161 162 def isDiv: Boolean = fuType == FuType.div 163 164 def isCsr: Boolean = fuType == FuType.csr 165 166 def isFence: Boolean = fuType == FuType.fence 167 168 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 169 fuType == FuType.vppu || fuType == FuType.vipu || 170 fuType == FuType.vfalu || fuType == FuType.vfma || 171 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 172 fuType == FuType.vidiv 173 174 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 175 176 def isSta: Boolean = name.contains("sta") 177 178 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 179 fuType == FuType.div || fuType == FuType.fDivSqrt || 180 fuType == FuType.vfdiv || fuType == FuType.vidiv 181 182 /** 183 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 184 * @param data [[DataConfig]] 185 * @param tips tips if get failed 186 * @return the index of special src data 187 */ 188 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 189 val srcIdxVec = srcData.map(x => x.indexOf(data)) 190 val idx0 = srcIdxVec.head 191 for (idx <- srcIdxVec) { 192 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 193 } 194 idx0 195 } 196 197 override def toString: String = { 198 var str = s"${this.name}: " 199 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 200 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 201 str += s"latency($latency)" 202 str += s"src($srcData)" 203 str 204 } 205} 206 207object FuConfig { 208 val JmpCfg: FuConfig = FuConfig ( 209 name = "jmp", 210 fuType = FuType.jmp, 211 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 212 srcData = Seq( 213 Seq(IntData()), // jal 214 ), 215 piped = true, 216 writeIntRf = true, 217 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 218 ) 219 220 val BrhCfg: FuConfig = FuConfig ( 221 name = "brh", 222 fuType = FuType.brh, 223 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 224 srcData = Seq( 225 Seq(IntData(), IntData()), 226 ), 227 piped = true, 228 immType = Set(SelImm.IMM_SB), 229 ) 230 231 val I2fCfg: FuConfig = FuConfig ( 232 name = "i2f", 233 FuType.i2f, 234 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 235 srcData = Seq( 236 Seq(IntData()), 237 ), 238 piped = true, 239 writeFpRf = true, 240 writeFflags = true, 241 latency = CertainLatency(2), 242 needSrcFrm = true, 243 ) 244 245 val I2vCfg: FuConfig = FuConfig ( 246 name = "i2v", 247 FuType.i2v, 248 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 249 srcData = Seq( 250 Seq(IntData(), IntData()), 251 ), 252 piped = true, 253 writeFpRf = true, 254 writeVecRf = true, 255 latency = CertainLatency(0), 256 dataBits = 128, 257 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 258 ) 259 260 val F2vCfg: FuConfig = FuConfig ( 261 name = "f2v", 262 FuType.f2v, 263 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 264 srcData = Seq( 265 Seq(FpData(), FpData()), 266 Seq(FpData()), 267 ), 268 piped = true, 269 writeVecRf = true, 270 latency = CertainLatency(0), 271 dataBits = 128, 272 ) 273 274 val CsrCfg: FuConfig = FuConfig ( 275 name = "csr", 276 fuType = FuType.csr, 277 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 278 srcData = Seq( 279 Seq(IntData()), 280 ), 281 piped = true, 282 writeIntRf = true, 283 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 284 flushPipe = true, 285 ) 286 287 val AluCfg: FuConfig = FuConfig ( 288 name = "alu", 289 fuType = FuType.alu, 290 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 291 srcData = Seq( 292 Seq(IntData(), IntData()), 293 ), 294 piped = true, 295 writeIntRf = true, 296 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 297 ) 298 299 val MulCfg: FuConfig = FuConfig ( 300 name = "mul", 301 fuType = FuType.mul, 302 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 303 srcData = Seq( 304 Seq(IntData(), IntData()), 305 ), 306 piped = true, 307 writeIntRf = true, 308 latency = CertainLatency(2), 309 ) 310 311 val DivCfg: FuConfig = FuConfig ( 312 name = "div", 313 fuType = FuType.div, 314 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 315 srcData = Seq( 316 Seq(IntData(), IntData()), 317 ), 318 piped = false, 319 writeIntRf = true, 320 latency = UncertainLatency(), 321 hasInputBuffer = (true, 4, true) 322 ) 323 324 val FenceCfg: FuConfig = FuConfig ( 325 name = "fence", 326 FuType.fence, 327 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 328 srcData = Seq( 329 Seq(IntData(), IntData()), 330 ), 331 piped = true, 332 latency = CertainLatency(0), 333 exceptionOut = Seq(illegalInstr, virtualInstr), 334 flushPipe = true 335 ) 336 337 // Todo: split it to simple bitmap exu and complex bku 338 val BkuCfg: FuConfig = FuConfig ( 339 name = "bku", 340 fuType = FuType.bku, 341 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 342 srcData = Seq( 343 Seq(IntData(), IntData()), 344 ), 345 piped = true, 346 writeIntRf = true, 347 latency = CertainLatency(2), 348 ) 349 350 val VSetRvfWvfCfg: FuConfig = FuConfig( 351 name = "vsetrvfwvf", 352 fuType = FuType.vsetfwf, 353 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 354 srcData = Seq( 355 Seq(VecData(), VecData()), 356 ), 357 piped = true, 358 writeVecRf = true, 359 writeVConfig = true, 360 writeVType = true, 361 latency = CertainLatency(0), 362 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 363 ) 364 365 val VSetRiWvfCfg: FuConfig = FuConfig( 366 name = "vsetriwvf", 367 fuType = FuType.vsetiwf, 368 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 369 srcData = Seq( 370 Seq(IntData(), IntData()), 371 ), 372 piped = true, 373 writeVecRf = true, 374 writeVConfig = true, 375 writeVType = true, 376 latency = CertainLatency(0), 377 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 378 ) 379 380 val VSetRiWiCfg: FuConfig = FuConfig( 381 name = "vsetriwi", 382 fuType = FuType.vsetiwi, 383 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 384 srcData = Seq( 385 Seq(IntData(), IntData()), 386 ), 387 piped = true, 388 writeIntRf = true, 389 latency = CertainLatency(0), 390 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 391 ) 392 393 val LduCfg: FuConfig = FuConfig ( 394 name = "ldu", 395 fuType = FuType.ldu, 396 fuGen = null, // Todo 397 srcData = Seq( 398 Seq(IntData()), 399 ), 400 piped = false, // Todo: check it 401 writeIntRf = true, 402 writeFpRf = true, 403 latency = UncertainLatency(3), 404 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 405 flushPipe = true, 406 replayInst = true, 407 hasLoadError = true, 408 trigger = true, 409 immType = Set(SelImm.IMM_I), 410 ) 411 412 val StaCfg: FuConfig = FuConfig ( 413 name = "sta", 414 fuType = FuType.stu, 415 fuGen = null, // Todo 416 srcData = Seq( 417 Seq(IntData()), 418 ), 419 piped = false, 420 latency = UncertainLatency(), 421 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 422 trigger = true, 423 immType = Set(SelImm.IMM_S), 424 ) 425 426 val StdCfg: FuConfig = FuConfig ( 427 name = "std", 428 fuType = FuType.stu, 429 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 430 srcData = Seq( 431 Seq(IntData()), 432 Seq(FpData()), 433 ), 434 piped = true, 435 latency = CertainLatency(0) 436 ) 437 438 val HyldaCfg = FuConfig ( 439 name = "hylda", 440 fuType = FuType.ldu, 441 fuGen = null, // Todo 442 srcData = Seq( 443 Seq(IntData()), 444 ), 445 piped = false, // Todo: check it 446 writeIntRf = true, 447 writeFpRf = true, 448 latency = UncertainLatency(3), 449 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 450 flushPipe = true, 451 replayInst = true, 452 hasLoadError = true, 453 immType = Set(SelImm.IMM_I), 454 ) 455 456 val HystaCfg = FuConfig ( 457 name = "hysta", 458 fuType = FuType.stu, 459 fuGen = null, // Todo 460 srcData = Seq( 461 Seq(IntData()), 462 ), 463 piped = false, 464 latency = UncertainLatency(), 465 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 466 immType = Set(SelImm.IMM_S), 467 ) 468 469 val FakeHystaCfg = FuConfig ( 470 name = "hysta", 471 fuType = FuType.stu, 472 fuGen = null, // Todo 473 srcData = Seq(), 474 piped = false, 475 latency = UncertainLatency(), 476 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 477 immType = Set(), 478 ) 479 480 val MouCfg: FuConfig = FuConfig ( 481 name = "mou", 482 fuType = FuType.mou, 483 fuGen = null, // Todo 484 srcData = Seq( 485 Seq(IntData()), 486 ), 487 piped = false, // Todo: check it 488 writeFakeIntRf = true, 489 latency = UncertainLatency(), 490 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 491 trigger = true, 492 ) 493 494 val MoudCfg: FuConfig = FuConfig ( 495 name = "moud", 496 fuType = FuType.mou, 497 fuGen = null, // Todo 498 srcData = Seq( 499 Seq(IntData()), 500 ), 501 piped = true, 502 latency = CertainLatency(0), 503 ) 504 505 val VialuCfg = FuConfig ( 506 name = "vialuFix", 507 fuType = FuType.vialuF, 508 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 509 srcData = Seq( 510 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 511 ), 512 piped = true, 513 writeVecRf = true, 514 writeVxsat = true, 515 needSrcVxrm = true, 516 latency = CertainLatency(1), 517 vconfigWakeUp = true, 518 maskWakeUp = true, 519 dataBits = 128, 520 exceptionOut = Seq(illegalInstr), 521 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 522 ) 523 524 val VimacCfg = FuConfig ( 525 name = "vimac", 526 fuType = FuType.vimac, 527 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 528 srcData = Seq( 529 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 530 ), 531 piped = true, 532 writeVecRf = true, 533 writeVxsat = true, 534 needSrcVxrm = true, 535 latency = CertainLatency(2), 536 vconfigWakeUp = true, 537 maskWakeUp = true, 538 dataBits = 128, 539 exceptionOut = Seq(illegalInstr), 540 ) 541 542 val VidivCfg = FuConfig ( 543 name = "vidiv", 544 fuType = FuType.vidiv, 545 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 546 srcData = Seq( 547 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 548 ), 549 piped = false, 550 writeVecRf = true, 551 latency = UncertainLatency(), 552 vconfigWakeUp = true, 553 maskWakeUp = true, 554 dataBits = 128, 555 exceptionOut = Seq(illegalInstr), 556 ) 557 558 val VppuCfg = FuConfig ( 559 name = "vppu", 560 fuType = FuType.vppu, 561 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 562 srcData = Seq( 563 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 564 ), 565 piped = true, 566 writeVecRf = true, 567 latency = CertainLatency(2), 568 vconfigWakeUp = true, 569 maskWakeUp = true, 570 dataBits = 128, 571 exceptionOut = Seq(illegalInstr), 572 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 573 ) 574 575 val VipuCfg: FuConfig = FuConfig ( 576 name = "vipu", 577 fuType = FuType.vipu, 578 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 579 srcData = Seq( 580 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 581 ), 582 piped = true, 583 writeIntRf = true, 584 writeVecRf = true, 585 latency = CertainLatency(2), 586 vconfigWakeUp = true, 587 maskWakeUp = true, 588 dataBits = 128, 589 exceptionOut = Seq(illegalInstr), 590 ) 591 592 val VfaluCfg = FuConfig ( 593 name = "vfalu", 594 fuType = FuType.vfalu, 595 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 596 srcData = Seq( 597 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 598 ), 599 piped = true, 600 writeVecRf = true, 601 writeFpRf = true, 602 writeFflags = true, 603 latency = CertainLatency(1), 604 vconfigWakeUp = true, 605 maskWakeUp = true, 606 dataBits = 128, 607 exceptionOut = Seq(illegalInstr), 608 needSrcFrm = true, 609 ) 610 611 val VfmaCfg = FuConfig ( 612 name = "vfma", 613 fuType = FuType.vfma, 614 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 615 srcData = Seq( 616 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 617 ), 618 piped = true, 619 writeVecRf = true, 620 writeFflags = true, 621 latency = CertainLatency(3), 622 vconfigWakeUp = true, 623 maskWakeUp = true, 624 dataBits = 128, 625 exceptionOut = Seq(illegalInstr), 626 needSrcFrm = true, 627 ) 628 629 val VfdivCfg = FuConfig( 630 name = "vfdiv", 631 fuType = FuType.vfdiv, 632 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 633 srcData = Seq( 634 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 635 ), 636 piped = false, 637 writeVecRf = true, 638 writeFflags = true, 639 latency = UncertainLatency(), 640 vconfigWakeUp = true, 641 maskWakeUp = true, 642 dataBits = 128, 643 exceptionOut = Seq(illegalInstr), 644 needSrcFrm = true, 645 ) 646 647 val VfcvtCfg = FuConfig( 648 name = "vfcvt", 649 fuType = FuType.vfcvt, 650 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 651 srcData = Seq( 652 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 653 ), 654 piped = true, 655 writeVecRf = true, 656 writeFflags = true, 657 latency = CertainLatency(2), 658 vconfigWakeUp = true, 659 maskWakeUp = true, 660 dataBits = 128, 661 exceptionOut = Seq(illegalInstr), 662 needSrcFrm = true, 663 ) 664 665 val FaluCfg = FuConfig( 666 name = "falu", 667 fuType = FuType.falu, 668 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 669 srcData = Seq( 670 Seq(FpData(), FpData()), 671 ), 672 piped = true, 673 writeFpRf = true, 674 writeIntRf = true, 675 writeFflags = true, 676 latency = CertainLatency(1), 677 dataBits = 64, 678 needSrcFrm = true, 679 ) 680 681 val FmacCfg = FuConfig( 682 name = "fmac", 683 fuType = FuType.fmac, 684 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 685 srcData = Seq( 686 Seq(FpData(), FpData(), FpData()), 687 ), 688 piped = true, 689 writeFpRf = true, 690 writeFflags = true, 691 latency = CertainLatency(3), 692 dataBits = 64, 693 needSrcFrm = true, 694 ) 695 696 val FdivCfg = FuConfig( 697 name = "fdiv", 698 fuType = FuType.fDivSqrt, 699 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 700 srcData = Seq( 701 Seq(FpData(), FpData()), 702 ), 703 piped = false, 704 writeFpRf = true, 705 writeFflags = true, 706 latency = UncertainLatency(), 707 dataBits = 64, 708 needSrcFrm = true, 709 ) 710 711 val FcvtCfg = FuConfig( 712 name = "fcvt", 713 fuType = FuType.fcvt, 714 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 715 srcData = Seq( 716 Seq(FpData()), 717 ), 718 piped = true, 719 writeFpRf = true, 720 writeIntRf = true, 721 writeFflags = true, 722 latency = CertainLatency(2), 723 dataBits = 64, 724 needSrcFrm = true, 725 ) 726 727 val VlduCfg: FuConfig = FuConfig ( 728 name = "vldu", 729 fuType = FuType.vldu, 730 fuGen = null, 731 srcData = Seq( 732 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 733 ), 734 piped = false, // Todo: check it 735 writeVecRf = true, 736 latency = UncertainLatency(), 737 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 738 flushPipe = true, 739 replayInst = true, 740 hasLoadError = true, 741 vconfigWakeUp = true, 742 maskWakeUp = true, 743 dataBits = 128, 744 ) 745 746 val VstuCfg: FuConfig = FuConfig ( 747 name = "vstu", 748 fuType = FuType.vstu, 749 fuGen = null, 750 srcData = Seq( 751 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 752 ), 753 piped = false, 754 writeVecRf = false, 755 latency = UncertainLatency(), 756 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 757 flushPipe = true, 758 replayInst = true, 759 hasLoadError = true, 760 vconfigWakeUp = true, 761 maskWakeUp = true, 762 dataBits = 128, 763 ) 764 765 val VseglduSeg: FuConfig = FuConfig ( 766 name = "vsegldu", 767 fuType = FuType.vsegldu, 768 fuGen = null, 769 srcData = Seq( 770 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 771 ), 772 piped = false, // Todo: check it 773 writeVecRf = true, 774 latency = UncertainLatency(), 775 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 776 flushPipe = true, 777 replayInst = true, 778 hasLoadError = true, 779 vconfigWakeUp = true, 780 maskWakeUp = true, 781 dataBits = 128, 782 ) 783 784 val VsegstuCfg: FuConfig = FuConfig( 785 name = "vsegstu", 786 fuType = FuType.vsegstu, 787 fuGen = null, 788 srcData = Seq( 789 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 790 ), 791 piped = false, 792 writeVecRf = false, 793 latency = UncertainLatency(), 794 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 795 flushPipe = true, 796 replayInst = true, 797 hasLoadError = true, 798 vconfigWakeUp = true, 799 maskWakeUp = true, 800 dataBits = 128, 801 ) 802 803 def allConfigs = Seq( 804 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 805 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 806 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 807 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 808 ) 809 810 def VecArithFuConfigs = Seq( 811 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 812 ) 813} 814 815