1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 138 139 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 140 141 // predict info 142 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 145 146 def needFPUCtrl: Boolean = { 147 import FuType._ 148 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 149 } 150 151 def needVecCtrl: Boolean = { 152 import FuType._ 153 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 154 } 155 156 def isMul: Boolean = fuType == FuType.mul 157 158 def isDiv: Boolean = fuType == FuType.div 159 160 def isCsr: Boolean = fuType == FuType.csr 161 162 def isFence: Boolean = fuType == FuType.fence 163 164 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 165 fuType == FuType.vppu || fuType == FuType.vipu || 166 fuType == FuType.vfalu || fuType == FuType.vfma || 167 fuType == FuType.vfdiv || fuType == FuType.vfcvt 168 169 def isSta: Boolean = name.contains("sta") 170 171 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 172 fuType == FuType.fmisc || fuType == FuType.div || 173 fuType == FuType.vfdiv 174 175 /** 176 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 177 * @param data [[DataConfig]] 178 * @param tips tips if get failed 179 * @return the index of special src data 180 */ 181 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 182 val srcIdxVec = srcData.map(x => x.indexOf(data)) 183 val idx0 = srcIdxVec.head 184 for (idx <- srcIdxVec) { 185 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 186 } 187 idx0 188 } 189 190 override def toString: String = { 191 var str = s"${this.name}: " 192 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 193 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 194 str += s"latency($latency)" 195 str += s"src($srcData)" 196 str 197 } 198} 199 200object FuConfig { 201 val JmpCfg: FuConfig = FuConfig ( 202 name = "jmp", 203 fuType = FuType.jmp, 204 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 205 srcData = Seq( 206 Seq(IntData()), // jal 207 ), 208 piped = true, 209 writeIntRf = true, 210 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 211 ) 212 213 val BrhCfg: FuConfig = FuConfig ( 214 name = "brh", 215 fuType = FuType.brh, 216 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 217 srcData = Seq( 218 Seq(IntData(), IntData()), 219 ), 220 piped = true, 221 immType = Set(SelImm.IMM_SB), 222 ) 223 224 val I2fCfg: FuConfig = FuConfig ( 225 name = "i2f", 226 FuType.i2f, 227 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 228 srcData = Seq( 229 Seq(IntData()), 230 ), 231 piped = true, 232 writeFpRf = true, 233 writeFflags = true, 234 latency = CertainLatency(2), 235 needSrcFrm = true, 236 ) 237 238 val I2vCfg: FuConfig = FuConfig ( 239 name = "i2v", 240 FuType.i2v, 241 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 242 srcData = Seq( 243 Seq(IntData(), IntData()), 244 ), 245 piped = true, 246 writeVecRf = true, 247 latency = CertainLatency(0), 248 dataBits = 128, 249 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 250 ) 251 252 val CsrCfg: FuConfig = FuConfig ( 253 name = "csr", 254 fuType = FuType.csr, 255 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 256 srcData = Seq( 257 Seq(IntData()), 258 ), 259 piped = true, 260 writeIntRf = true, 261 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 262 flushPipe = true, 263 ) 264 265 val AluCfg: FuConfig = FuConfig ( 266 name = "alu", 267 fuType = FuType.alu, 268 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 269 srcData = Seq( 270 Seq(IntData(), IntData()), 271 ), 272 piped = true, 273 writeIntRf = true, 274 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 275 ) 276 277 val MulCfg: FuConfig = FuConfig ( 278 name = "mul", 279 fuType = FuType.mul, 280 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 281 srcData = Seq( 282 Seq(IntData(), IntData()), 283 ), 284 piped = true, 285 writeIntRf = true, 286 latency = CertainLatency(2), 287 ) 288 289 val DivCfg: FuConfig = FuConfig ( 290 name = "div", 291 fuType = FuType.div, 292 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 293 srcData = Seq( 294 Seq(IntData(), IntData()), 295 ), 296 piped = false, 297 writeIntRf = true, 298 latency = UncertainLatency(), 299 hasInputBuffer = (true, 4, true) 300 ) 301 302 val FenceCfg: FuConfig = FuConfig ( 303 name = "fence", 304 FuType.fence, 305 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 306 srcData = Seq( 307 Seq(IntData(), IntData()), 308 ), 309 piped = true, 310 latency = CertainLatency(0), 311 exceptionOut = Seq(illegalInstr), 312 flushPipe = true 313 ) 314 315 // Todo: split it to simple bitmap exu and complex bku 316 val BkuCfg: FuConfig = FuConfig ( 317 name = "bku", 318 fuType = FuType.bku, 319 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 320 srcData = Seq( 321 Seq(IntData(), IntData()), 322 ), 323 piped = true, 324 writeIntRf = true, 325 latency = CertainLatency(2), 326 ) 327 328 val VSetRvfWvfCfg: FuConfig = FuConfig( 329 name = "vsetrvfwvf", 330 fuType = FuType.vsetfwf, 331 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 332 srcData = Seq( 333 Seq(FpData(), FpData()), 334 ), 335 piped = true, 336 writeVecRf = true, 337 latency = CertainLatency(0), 338 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 339 ) 340 341 val VSetRiWvfCfg: FuConfig = FuConfig( 342 name = "vsetriwvf", 343 fuType = FuType.vsetiwf, 344 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 345 srcData = Seq( 346 Seq(IntData(), IntData()), 347 ), 348 piped = true, 349 writeVecRf = true, 350 latency = CertainLatency(0), 351 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 352 ) 353 354 val VSetRiWiCfg: FuConfig = FuConfig( 355 name = "vsetriwi", 356 fuType = FuType.vsetiwi, 357 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 358 srcData = Seq( 359 Seq(IntData(), IntData()), 360 ), 361 piped = true, 362 writeIntRf = true, 363 latency = CertainLatency(0), 364 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 365 ) 366 367 val FmacCfg: FuConfig = FuConfig ( 368 name = "fmac", 369 fuType = FuType.fmac, 370 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 371 srcData = Seq( 372 Seq(FpData(), FpData()), 373 Seq(FpData(), FpData(), FpData()), 374 ), 375 piped = false, 376 writeFpRf = true, 377 writeFflags = true, 378 latency = UncertainLatency(), 379 needSrcFrm = true, 380 ) 381 382 val F2iCfg: FuConfig = FuConfig ( 383 name = "f2i", 384 fuType = FuType.fmisc, 385 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 386 srcData = Seq( 387 Seq(FpData(), FpData()), 388 Seq(FpData()), 389 ), 390 piped = true, 391 writeIntRf = true, 392 writeFflags = true, 393 latency = CertainLatency(2), 394 needSrcFrm = true, 395 ) 396 397 val F2fCfg: FuConfig = FuConfig ( 398 name = "f2f", 399 fuType = FuType.fmisc, 400 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 401 srcData = Seq( 402 Seq(FpData(), FpData()), 403 Seq(FpData()), 404 ), 405 piped = true, 406 writeFpRf = true, 407 writeFflags = true, 408 latency = CertainLatency(2), 409 needSrcFrm = true, 410 ) 411 412 val FDivSqrtCfg: FuConfig = FuConfig ( 413 name = "fDivSqrt", 414 fuType = FuType.fDivSqrt, 415 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 416 srcData = Seq( 417 Seq(FpData(), FpData()), 418 ), 419 piped = false, 420 writeFpRf = true, 421 writeFflags = true, 422 latency = UncertainLatency(), 423 hasInputBuffer = (true, 8, true), 424 needSrcFrm = true, 425 ) 426 427 val LduCfg: FuConfig = FuConfig ( 428 name = "ldu", 429 fuType = FuType.ldu, 430 fuGen = null, // Todo 431 srcData = Seq( 432 Seq(IntData()), 433 ), 434 piped = false, // Todo: check it 435 writeIntRf = true, 436 writeFpRf = true, 437 latency = UncertainLatency(3), 438 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 439 flushPipe = true, 440 replayInst = true, 441 hasLoadError = true, 442 trigger = true, 443 immType = Set(SelImm.IMM_I), 444 ) 445 446 val StaCfg: FuConfig = FuConfig ( 447 name = "sta", 448 fuType = FuType.stu, 449 fuGen = null, // Todo 450 srcData = Seq( 451 Seq(IntData()), 452 ), 453 piped = false, 454 latency = UncertainLatency(), 455 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 456 trigger = true, 457 immType = Set(SelImm.IMM_S), 458 ) 459 460 val StdCfg: FuConfig = FuConfig ( 461 name = "std", 462 fuType = FuType.stu, 463 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 464 srcData = Seq( 465 Seq(IntData()), 466 Seq(FpData()), 467 ), 468 piped = true, 469 latency = CertainLatency(0) 470 ) 471 472 val HyldaCfg = FuConfig ( 473 name = "hylda", 474 fuType = FuType.ldu, 475 fuGen = null, // Todo 476 srcData = Seq( 477 Seq(IntData()), 478 ), 479 piped = false, // Todo: check it 480 writeIntRf = true, 481 writeFpRf = true, 482 latency = UncertainLatency(3), 483 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 484 flushPipe = true, 485 replayInst = true, 486 hasLoadError = true, 487 immType = Set(SelImm.IMM_I), 488 ) 489 490 val HystaCfg = FuConfig ( 491 name = "hysta", 492 fuType = FuType.stu, 493 fuGen = null, // Todo 494 srcData = Seq( 495 Seq(IntData()), 496 ), 497 piped = false, 498 latency = UncertainLatency(), 499 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 500 immType = Set(SelImm.IMM_S), 501 ) 502 503 val FakeHystaCfg = FuConfig ( 504 name = "hysta", 505 fuType = FuType.stu, 506 fuGen = null, // Todo 507 srcData = Seq(), 508 piped = false, 509 latency = UncertainLatency(), 510 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 511 immType = Set(), 512 ) 513 514 val MouCfg: FuConfig = FuConfig ( 515 name = "mou", 516 fuType = FuType.mou, 517 fuGen = null, // Todo 518 srcData = Seq( 519 Seq(IntData()), 520 ), 521 piped = false, // Todo: check it 522 writeIntRf = true, 523 latency = UncertainLatency(), 524 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 525 trigger = true, 526 ) 527 528 val MoudCfg: FuConfig = FuConfig ( 529 name = "moud", 530 fuType = FuType.mou, 531 fuGen = null, // Todo 532 srcData = Seq( 533 Seq(IntData()), 534 ), 535 piped = true, 536 latency = CertainLatency(0), 537 ) 538 539 val VialuCfg = FuConfig ( 540 name = "vialuFix", 541 fuType = FuType.vialuF, 542 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 543 srcData = Seq( 544 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 545 ), 546 piped = true, 547 writeVecRf = true, 548 writeVxsat = true, 549 latency = CertainLatency(1), 550 vconfigWakeUp = true, 551 maskWakeUp = true, 552 dataBits = 128, 553 exceptionOut = Seq(illegalInstr), 554 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 555 ) 556 557 val VimacCfg = FuConfig ( 558 name = "vimac", 559 fuType = FuType.vimac, 560 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 561 srcData = Seq( 562 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 563 ), 564 piped = true, 565 writeVecRf = true, 566 writeVxsat = true, 567 latency = CertainLatency(2), 568 vconfigWakeUp = true, 569 maskWakeUp = true, 570 dataBits = 128, 571 exceptionOut = Seq(illegalInstr), 572 ) 573 574 val VppuCfg = FuConfig ( 575 name = "vppu", 576 fuType = FuType.vppu, 577 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 578 srcData = Seq( 579 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 580 ), 581 piped = true, 582 writeVecRf = true, 583 writeVxsat = true, 584 latency = CertainLatency(1), 585 vconfigWakeUp = true, 586 maskWakeUp = true, 587 dataBits = 128, 588 exceptionOut = Seq(illegalInstr), 589 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 590 ) 591 592 val VipuCfg: FuConfig = FuConfig ( 593 name = "vipu", 594 fuType = FuType.vipu, 595 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 596 srcData = Seq( 597 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 598 ), 599 piped = true, 600 writeIntRf = true, 601 writeVecRf = true, 602 latency = CertainLatency(1), 603 vconfigWakeUp = true, 604 maskWakeUp = true, 605 dataBits = 128, 606 exceptionOut = Seq(illegalInstr), 607 ) 608 609 val VfaluCfg = FuConfig ( 610 name = "vfalu", 611 fuType = FuType.vfalu, 612 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 613 srcData = Seq( 614 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 615 ), 616 piped = true, 617 writeVecRf = true, 618 writeFpRf = true, 619 writeIntRf = true, 620 writeFflags = true, 621 latency = CertainLatency(1), 622 vconfigWakeUp = true, 623 maskWakeUp = true, 624 dataBits = 128, 625 exceptionOut = Seq(illegalInstr), 626 ) 627 628 val VfmaCfg = FuConfig ( 629 name = "vfma", 630 fuType = FuType.vfma, 631 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 632 srcData = Seq( 633 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 634 ), 635 piped = true, 636 writeVecRf = true, 637 writeFpRf = true, 638 writeFflags = true, 639 latency = CertainLatency(3), 640 vconfigWakeUp = true, 641 maskWakeUp = true, 642 dataBits = 128, 643 exceptionOut = Seq(illegalInstr), 644 ) 645 646 val VfdivCfg = FuConfig( 647 name = "vfdiv", 648 fuType = FuType.vfdiv, 649 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 650 srcData = Seq( 651 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 652 ), 653 piped = false, 654 writeVecRf = true, 655 writeFpRf = true, 656 writeFflags = true, 657 latency = UncertainLatency(), 658 vconfigWakeUp = true, 659 maskWakeUp = true, 660 dataBits = 128, 661 exceptionOut = Seq(illegalInstr), 662 ) 663 664 val VfcvtCfg = FuConfig( 665 name = "vfcvt", 666 fuType = FuType.vfcvt, 667 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 668 srcData = Seq( 669 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 670 ), 671 piped = true, 672 writeVecRf = true, 673 writeFpRf = false, 674 writeFflags = true, 675 latency = CertainLatency(2), 676 vconfigWakeUp = true, 677 maskWakeUp = true, 678 dataBits = 128, 679 exceptionOut = Seq(illegalInstr), 680 ) 681 682 683 val VlduCfg: FuConfig = FuConfig ( 684 name = "vldu", 685 fuType = FuType.vldu, 686 fuGen = null, 687 srcData = Seq( 688 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 689 ), 690 piped = false, // Todo: check it 691 writeVecRf = true, 692 latency = UncertainLatency(), 693 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 694 flushPipe = true, 695 replayInst = true, 696 hasLoadError = true, 697 vconfigWakeUp = true, 698 maskWakeUp = true, 699 dataBits = 128, 700 ) 701 702 val VstuCfg: FuConfig = FuConfig ( 703 name = "vstu", 704 fuType = FuType.vstu, 705 fuGen = null, 706 srcData = Seq( 707 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 708 ), 709 piped = false, 710 writeVecRf = false, 711 latency = UncertainLatency(), 712 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 713 flushPipe = true, 714 replayInst = true, 715 hasLoadError = true, 716 vconfigWakeUp = true, 717 maskWakeUp = true, 718 dataBits = 128, 719 ) 720 721 def allConfigs = Seq( 722 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 723 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 724 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 725 ) 726 727 def VecArithFuConfigs = Seq( 728 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 729 ) 730} 731 732