1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect is in its exception bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isFence: Boolean = fuType == FuType.fence 174 175 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 176 fuType == FuType.vppu || fuType == FuType.vipu || 177 fuType == FuType.vfalu || fuType == FuType.vfma || 178 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 179 fuType == FuType.vidiv 180 181 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf 182 183 def isSta: Boolean = name.contains("sta") 184 185 def ckAlwaysEn: Boolean = isCsr || isFence 186 187 /** 188 * Get index of special src data, like [[VlData]], [[V0Data]] 189 * 190 * @param data [[DataConfig]] 191 * @param tips tips if get failed 192 * @return the index of special src data 193 */ 194 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 195 val srcIdxVec = srcData.map(x => x.indexOf(data)) 196 val idx0 = srcIdxVec.head 197 for (idx <- srcIdxVec) { 198 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 199 } 200 idx0 201 } 202 203 override def toString: String = { 204 var str = s"${this.name}: " 205 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 206 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 207 str += s"latency($latency)" 208 str += s"src($srcData)" 209 str 210 } 211} 212 213object FuConfig { 214 val JmpCfg: FuConfig = FuConfig ( 215 name = "jmp", 216 fuType = FuType.jmp, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 218 srcData = Seq( 219 Seq(IntData()), // jal 220 ), 221 piped = true, 222 writeIntRf = true, 223 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 224 ) 225 226 val BrhCfg: FuConfig = FuConfig ( 227 name = "brh", 228 fuType = FuType.brh, 229 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 230 srcData = Seq( 231 Seq(IntData(), IntData()), 232 ), 233 piped = true, 234 immType = Set(SelImm.IMM_SB), 235 ) 236 237 val I2fCfg: FuConfig = FuConfig ( 238 name = "i2f", 239 FuType.i2f, 240 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 241 srcData = Seq( 242 Seq(IntData()), 243 ), 244 piped = true, 245 writeFpRf = true, 246 writeFflags = true, 247 latency = CertainLatency(2), 248 needSrcFrm = true, 249 ) 250 251 val I2vCfg: FuConfig = FuConfig ( 252 name = "i2v", 253 FuType.i2v, 254 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 255 srcData = Seq( 256 Seq(IntData(), IntData()), 257 ), 258 piped = true, 259 writeFpRf = true, 260 writeVecRf = true, 261 writeV0Rf = true, 262 latency = CertainLatency(0), 263 destDataBits = 128, 264 srcDataBits = Some(64), 265 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 266 ) 267 268 val F2vCfg: FuConfig = FuConfig ( 269 name = "f2v", 270 FuType.f2v, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 272 srcData = Seq( 273 Seq(FpData(), FpData()), 274 Seq(FpData()), 275 ), 276 piped = true, 277 writeVecRf = true, 278 writeV0Rf = true, 279 latency = CertainLatency(0), 280 destDataBits = 128, 281 srcDataBits = Some(64), 282 ) 283 284 val CsrCfg: FuConfig = FuConfig ( 285 name = "csr", 286 fuType = FuType.csr, 287 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 288 srcData = Seq( 289 Seq(IntData()), 290 ), 291 piped = true, 292 writeIntRf = true, 293 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 294 flushPipe = true, 295 ) 296 297 val AluCfg: FuConfig = FuConfig ( 298 name = "alu", 299 fuType = FuType.alu, 300 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 301 srcData = Seq( 302 Seq(IntData(), IntData()), 303 ), 304 piped = true, 305 writeIntRf = true, 306 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 307 ) 308 309 val MulCfg: FuConfig = FuConfig ( 310 name = "mul", 311 fuType = FuType.mul, 312 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 313 srcData = Seq( 314 Seq(IntData(), IntData()), 315 ), 316 piped = true, 317 writeIntRf = true, 318 latency = CertainLatency(2), 319 ) 320 321 val DivCfg: FuConfig = FuConfig ( 322 name = "div", 323 fuType = FuType.div, 324 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 325 srcData = Seq( 326 Seq(IntData(), IntData()), 327 ), 328 piped = false, 329 writeIntRf = true, 330 latency = UncertainLatency(), 331 hasInputBuffer = (true, 4, true) 332 ) 333 334 val FenceCfg: FuConfig = FuConfig ( 335 name = "fence", 336 FuType.fence, 337 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 338 srcData = Seq( 339 Seq(IntData(), IntData()), 340 ), 341 piped = true, 342 latency = CertainLatency(0), 343 exceptionOut = Seq(illegalInstr, virtualInstr), 344 flushPipe = true 345 ) 346 347 // Todo: split it to simple bitmap exu and complex bku 348 val BkuCfg: FuConfig = FuConfig ( 349 name = "bku", 350 fuType = FuType.bku, 351 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 352 srcData = Seq( 353 Seq(IntData(), IntData()), 354 ), 355 piped = true, 356 writeIntRf = true, 357 latency = CertainLatency(2), 358 ) 359 360 val VSetRvfWvfCfg: FuConfig = FuConfig( 361 name = "vsetrvfwvf", 362 fuType = FuType.vsetfwf, 363 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 364 srcData = Seq( 365 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 366 ), 367 piped = true, 368 writeVlRf = true, 369 writeVType = true, 370 writeIntRf = true, 371 latency = CertainLatency(0), 372 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 373 ) 374 375 val VSetRiWvfCfg: FuConfig = FuConfig( 376 name = "vsetriwvf", 377 fuType = FuType.vsetiwf, 378 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 379 srcData = Seq( 380 Seq(IntData(), IntData()), 381 ), 382 piped = true, 383 writeVlRf = true, 384 writeVType = true, 385 latency = CertainLatency(0), 386 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 387 ) 388 389 val VSetRiWiCfg: FuConfig = FuConfig( 390 name = "vsetriwi", 391 fuType = FuType.vsetiwi, 392 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 393 srcData = Seq( 394 Seq(IntData(), IntData()), 395 ), 396 piped = true, 397 writeIntRf = true, 398 latency = CertainLatency(0), 399 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 400 ) 401 402 val LduCfg: FuConfig = FuConfig ( 403 name = "ldu", 404 fuType = FuType.ldu, 405 fuGen = null, // Todo 406 srcData = Seq( 407 Seq(IntData()), 408 ), 409 piped = false, // Todo: check it 410 writeIntRf = true, 411 writeFpRf = true, 412 latency = UncertainLatency(3), 413 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 414 flushPipe = true, 415 replayInst = true, 416 hasLoadError = true, 417 trigger = true, 418 immType = Set(SelImm.IMM_I), 419 ) 420 421 val StaCfg: FuConfig = FuConfig ( 422 name = "sta", 423 fuType = FuType.stu, 424 fuGen = null, // Todo 425 srcData = Seq( 426 Seq(IntData()), 427 ), 428 piped = false, 429 latency = UncertainLatency(), 430 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 431 trigger = true, 432 immType = Set(SelImm.IMM_S), 433 ) 434 435 val StdCfg: FuConfig = FuConfig ( 436 name = "std", 437 fuType = FuType.stu, 438 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 439 srcData = Seq( 440 Seq(IntData()), 441 Seq(FpData()), 442 ), 443 piped = true, 444 latency = CertainLatency(0) 445 ) 446 447 val HyldaCfg = FuConfig ( 448 name = "hylda", 449 fuType = FuType.ldu, 450 fuGen = null, // Todo 451 srcData = Seq( 452 Seq(IntData()), 453 ), 454 piped = false, // Todo: check it 455 writeIntRf = true, 456 writeFpRf = true, 457 latency = UncertainLatency(3), 458 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 459 flushPipe = true, 460 replayInst = true, 461 hasLoadError = true, 462 immType = Set(SelImm.IMM_I), 463 ) 464 465 val HystaCfg = FuConfig ( 466 name = "hysta", 467 fuType = FuType.stu, 468 fuGen = null, // Todo 469 srcData = Seq( 470 Seq(IntData()), 471 ), 472 piped = false, 473 latency = UncertainLatency(), 474 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 475 immType = Set(SelImm.IMM_S), 476 ) 477 478 val FakeHystaCfg = FuConfig ( 479 name = "hysta", 480 fuType = FuType.stu, 481 fuGen = null, // Todo 482 srcData = Seq(), 483 piped = false, 484 latency = UncertainLatency(), 485 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 486 immType = Set(), 487 ) 488 489 val MouCfg: FuConfig = FuConfig ( 490 name = "mou", 491 fuType = FuType.mou, 492 fuGen = null, // Todo 493 srcData = Seq( 494 Seq(IntData()), 495 ), 496 piped = false, // Todo: check it 497 writeFakeIntRf = true, 498 latency = UncertainLatency(), 499 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 500 trigger = true, 501 ) 502 503 val MoudCfg: FuConfig = FuConfig ( 504 name = "moud", 505 fuType = FuType.mou, 506 fuGen = null, // Todo 507 srcData = Seq( 508 Seq(IntData()), 509 ), 510 piped = true, 511 latency = CertainLatency(0), 512 ) 513 514 val VialuCfg = FuConfig ( 515 name = "vialuFix", 516 fuType = FuType.vialuF, 517 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 518 srcData = Seq( 519 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 520 ), 521 piped = true, 522 writeVecRf = true, 523 writeV0Rf = true, 524 writeVxsat = true, 525 needSrcVxrm = true, 526 latency = CertainLatency(1), 527 vconfigWakeUp = true, 528 maskWakeUp = true, 529 destDataBits = 128, 530 exceptionOut = Seq(illegalInstr), 531 ) 532 533 val VimacCfg = FuConfig ( 534 name = "vimac", 535 fuType = FuType.vimac, 536 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 537 srcData = Seq( 538 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 539 ), 540 piped = true, 541 writeVecRf = true, 542 writeV0Rf = true, 543 writeVxsat = true, 544 needSrcVxrm = true, 545 latency = CertainLatency(2), 546 vconfigWakeUp = true, 547 maskWakeUp = true, 548 destDataBits = 128, 549 exceptionOut = Seq(illegalInstr), 550 ) 551 552 val VidivCfg = FuConfig ( 553 name = "vidiv", 554 fuType = FuType.vidiv, 555 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 556 srcData = Seq( 557 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 558 ), 559 piped = false, 560 writeVecRf = true, 561 writeV0Rf = true, 562 latency = UncertainLatency(), 563 vconfigWakeUp = true, 564 maskWakeUp = true, 565 destDataBits = 128, 566 exceptionOut = Seq(illegalInstr), 567 ) 568 569 val VppuCfg = FuConfig ( 570 name = "vppu", 571 fuType = FuType.vppu, 572 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 573 srcData = Seq( 574 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 575 ), 576 piped = true, 577 writeVecRf = true, 578 writeV0Rf = true, 579 latency = CertainLatency(2), 580 vconfigWakeUp = true, 581 maskWakeUp = true, 582 destDataBits = 128, 583 exceptionOut = Seq(illegalInstr), 584 ) 585 586 val VipuCfg: FuConfig = FuConfig ( 587 name = "vipu", 588 fuType = FuType.vipu, 589 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 590 srcData = Seq( 591 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 592 ), 593 piped = true, 594 writeIntRf = true, 595 writeVecRf = true, 596 writeV0Rf = true, 597 latency = CertainLatency(2), 598 vconfigWakeUp = true, 599 maskWakeUp = true, 600 destDataBits = 128, 601 exceptionOut = Seq(illegalInstr), 602 ) 603 604 val VfaluCfg = FuConfig ( 605 name = "vfalu", 606 fuType = FuType.vfalu, 607 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 608 srcData = Seq( 609 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 610 ), 611 piped = true, 612 writeVecRf = true, 613 writeV0Rf = true, 614 writeFpRf = true, 615 writeFflags = true, 616 latency = CertainLatency(1), 617 vconfigWakeUp = true, 618 maskWakeUp = true, 619 destDataBits = 128, 620 exceptionOut = Seq(illegalInstr), 621 needSrcFrm = true, 622 ) 623 624 val VfmaCfg = FuConfig ( 625 name = "vfma", 626 fuType = FuType.vfma, 627 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 628 srcData = Seq( 629 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 630 ), 631 piped = true, 632 writeVecRf = true, 633 writeV0Rf = true, 634 writeFflags = true, 635 latency = CertainLatency(3), 636 vconfigWakeUp = true, 637 maskWakeUp = true, 638 destDataBits = 128, 639 exceptionOut = Seq(illegalInstr), 640 needSrcFrm = true, 641 ) 642 643 val VfdivCfg = FuConfig( 644 name = "vfdiv", 645 fuType = FuType.vfdiv, 646 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 647 srcData = Seq( 648 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 649 ), 650 piped = false, 651 writeVecRf = true, 652 writeV0Rf = true, 653 writeFflags = true, 654 latency = UncertainLatency(), 655 vconfigWakeUp = true, 656 maskWakeUp = true, 657 destDataBits = 128, 658 exceptionOut = Seq(illegalInstr), 659 needSrcFrm = true, 660 ) 661 662 val VfcvtCfg = FuConfig( 663 name = "vfcvt", 664 fuType = FuType.vfcvt, 665 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 666 srcData = Seq( 667 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 668 ), 669 piped = true, 670 writeVecRf = true, 671 writeV0Rf = true, 672 writeFflags = true, 673 latency = CertainLatency(2), 674 vconfigWakeUp = true, 675 maskWakeUp = true, 676 destDataBits = 128, 677 exceptionOut = Seq(illegalInstr), 678 needSrcFrm = true, 679 ) 680 681 val FaluCfg = FuConfig( 682 name = "falu", 683 fuType = FuType.falu, 684 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 685 srcData = Seq( 686 Seq(FpData(), FpData()), 687 ), 688 piped = true, 689 writeFpRf = true, 690 writeIntRf = true, 691 writeFflags = true, 692 latency = CertainLatency(1), 693 destDataBits = 64, 694 needSrcFrm = true, 695 ) 696 697 val FmacCfg = FuConfig( 698 name = "fmac", 699 fuType = FuType.fmac, 700 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 701 srcData = Seq( 702 Seq(FpData(), FpData(), FpData()), 703 ), 704 piped = true, 705 writeFpRf = true, 706 writeFflags = true, 707 latency = CertainLatency(3), 708 destDataBits = 64, 709 needSrcFrm = true, 710 ) 711 712 val FdivCfg = FuConfig( 713 name = "fdiv", 714 fuType = FuType.fDivSqrt, 715 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 716 srcData = Seq( 717 Seq(FpData(), FpData()), 718 ), 719 piped = false, 720 writeFpRf = true, 721 writeFflags = true, 722 latency = UncertainLatency(), 723 destDataBits = 64, 724 needSrcFrm = true, 725 ) 726 727 val FcvtCfg = FuConfig( 728 name = "fcvt", 729 fuType = FuType.fcvt, 730 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 731 srcData = Seq( 732 Seq(FpData()), 733 ), 734 piped = true, 735 writeFpRf = true, 736 writeIntRf = true, 737 writeFflags = true, 738 latency = CertainLatency(2), 739 destDataBits = 64, 740 needSrcFrm = true, 741 ) 742 743 val VlduCfg: FuConfig = FuConfig ( 744 name = "vldu", 745 fuType = FuType.vldu, 746 fuGen = null, 747 srcData = Seq( 748 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 749 ), 750 piped = false, // Todo: check it 751 writeVecRf = true, 752 writeV0Rf = true, 753 latency = UncertainLatency(), 754 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 755 flushPipe = true, 756 replayInst = true, 757 hasLoadError = true, 758 vconfigWakeUp = true, 759 maskWakeUp = true, 760 destDataBits = 128, 761 ) 762 763 val VstuCfg: FuConfig = FuConfig ( 764 name = "vstu", 765 fuType = FuType.vstu, 766 fuGen = null, 767 srcData = Seq( 768 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 769 ), 770 piped = false, 771 latency = UncertainLatency(), 772 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 773 flushPipe = true, 774 replayInst = true, 775 hasLoadError = true, 776 vconfigWakeUp = true, 777 maskWakeUp = true, 778 destDataBits = 128, 779 ) 780 781 val VseglduSeg: FuConfig = FuConfig ( 782 name = "vsegldu", 783 fuType = FuType.vsegldu, 784 fuGen = null, 785 srcData = Seq( 786 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 787 ), 788 piped = false, // Todo: check it 789 writeVecRf = true, 790 writeV0Rf = true, 791 latency = UncertainLatency(), 792 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 793 flushPipe = true, 794 replayInst = true, 795 hasLoadError = true, 796 vconfigWakeUp = true, 797 maskWakeUp = true, 798 destDataBits = 128, 799 ) 800 801 val VsegstuCfg: FuConfig = FuConfig( 802 name = "vsegstu", 803 fuType = FuType.vsegstu, 804 fuGen = null, 805 srcData = Seq( 806 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 807 ), 808 piped = false, 809 latency = UncertainLatency(), 810 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 811 flushPipe = true, 812 replayInst = true, 813 hasLoadError = true, 814 vconfigWakeUp = true, 815 maskWakeUp = true, 816 destDataBits = 128, 817 ) 818 819 def allConfigs = Seq( 820 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 821 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 822 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 823 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 824 ) 825 826 def VecArithFuConfigs = Seq( 827 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 828 ) 829} 830 831