1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import xiangshan.ExceptionNO.{illegalInstr, virtualInstr} 26 27class FenceToSbuffer extends Bundle { 28 val flushSb = Output(Bool()) 29 val sbIsEmpty = Input(Bool()) 30} 31 32class Fence(implicit p: Parameters) extends FunctionUnit { 33 34 val sfence = IO(Output(new SfenceBundle)) 35 val fencei = IO(Output(Bool())) 36 val toSbuffer = IO(new FenceToSbuffer) 37 val disableSfence = IO(Input(Bool())) 38 val disableHfenceg = IO(Input(Bool())) 39 val disableHfencev = IO(Input(Bool())) 40 val virtMode = IO(Input(Bool())) 41 val (valid, src1) = ( 42 io.in.valid, 43 io.in.bits.src(0) 44 ) 45 46 val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6) 47 48 val state = RegInit(s_idle) 49 /* fsm 50 * s_idle : init state, send sbflush 51 * s_wait : send sbflush, wait for sbEmpty 52 * s_tlb : flush tlb, just hold one cycle 53 * s_icache: flush icache, just hold one cycle 54 * s_fence : do nothing, for timing optimiaztion 55 * s_nofence: do nothing , for Svinval extension 56 */ 57 58 val sbuffer = toSbuffer.flushSb 59 val sbEmpty = toSbuffer.sbIsEmpty 60 val uop = RegEnable(io.in.bits.uop, io.in.fire) 61 val func = uop.ctrl.fuOpType 62 63 // NOTE: icache & tlb & sbuffer must receive flush signal at any time 64 sbuffer := state === s_wait && !(func === FenceOpType.sfence && disableSfence) 65 fencei := state === s_icache 66 sfence.valid := state === s_tlb && ((!disableSfence && func === FenceOpType.sfence) || (!disableHfencev && func === FenceOpType.hfence_v) || (!disableHfenceg && func === FenceOpType.hfence_g)) 67 sfence.bits.rs1 := uop.ctrl.imm(4, 0) === 0.U 68 sfence.bits.rs2 := uop.ctrl.imm(9, 5) === 0.U 69 sfence.bits.flushPipe := uop.ctrl.flushPipe 70 sfence.bits.hv := !disableHfencev && func === FenceOpType.hfence_v 71 sfence.bits.hg := !disableHfenceg && func === FenceOpType.hfence_g 72 XSError(sfence.valid && uop.ctrl.lsrc(0) =/= uop.ctrl.imm(4, 0), "lsrc0 is passed by imm\n") 73 XSError(sfence.valid && uop.ctrl.lsrc(1) =/= uop.ctrl.imm(9, 5), "lsrc1 is passed by imm\n") 74 val sfence_addr = Mux(sfence.bits.hg, io.in.bits.src(0) << 2, io.in.bits.src(0)) 75 sfence.bits.addr := RegEnable(sfence_addr, io.in.fire) 76 sfence.bits.id := RegEnable(io.in.bits.src(1), io.in.fire) 77 78 when (state === s_idle && io.in.valid) { state := s_wait } 79 when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache } 80 when (state === s_wait && ((func === FenceOpType.sfence && (sbEmpty || disableSfence)) 81 || (func === FenceOpType.hfence_g && (sbEmpty || disableHfenceg)) 82 || (func === FenceOpType.hfence_v && (sbEmpty || disableHfencev)))) { state := s_tlb } 83 when (state === s_wait && func === FenceOpType.fence && sbEmpty) { state := s_fence } 84 when (state === s_wait && func === FenceOpType.nofence && sbEmpty) { state := s_nofence } 85 when (state =/= s_idle && state =/= s_wait) { state := s_idle } 86 87 io.in.ready := state === s_idle 88 io.out.valid := state =/= s_idle && state =/= s_wait 89 io.out.bits.data := DontCare 90 io.out.bits.uop := uop 91 val illegalsfence = func === FenceOpType.sfence && disableSfence 92 val illegalhfenceg = func === FenceOpType.hfence_g && disableHfenceg 93 val illegalhfencev = func === FenceOpType.hfence_v && disableHfencev 94 io.out.bits.uop.cf.exceptionVec(illegalInstr) := (illegalsfence || illegalhfenceg || illegalhfencev) && !virtMode 95 io.out.bits.uop.cf.exceptionVec(virtualInstr) := (illegalsfence || illegalhfenceg || illegalhfencev) && virtMode 96 97 XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InrobIdx:${io.in.bits.uop.robIdx}\n") 98 XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n") 99 XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutrobIdx:${io.out.bits.uop.robIdx}\n") 100 101 assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen)) 102 assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true") 103} 104