xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala (revision 708ceed4afe43fb0ea3a52407e46b2794c573634) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import utils._
24
25class FenceToSbuffer extends Bundle {
26  val flushSb = Output(Bool())
27  val sbIsEmpty = Input(Bool())
28}
29
30class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
31
32  val sfence = IO(Output(new SfenceBundle))
33  val fencei = IO(Output(Bool()))
34  val toSbuffer = IO(new FenceToSbuffer)
35  val disableSfence = IO(Input(Bool()))
36
37  val (valid, src1) = (
38    io.in.valid,
39    io.in.bits.src(0)
40  )
41
42  val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: Nil = Enum(5)
43  val state = RegInit(s_idle)
44  /* fsm
45   * s_idle    : init state, send sbflush
46   * s_wait  : send sbflush, wait for sbEmpty
47   * s_tlb   : flush tlb, just hold one cycle
48   * s_icache: flush icache, just hold one cycle
49   * s_fence : do nothing, for timing optimiaztion
50   */
51
52  val sbuffer = toSbuffer.flushSb
53  val sbEmpty = toSbuffer.sbIsEmpty
54  val uop = RegEnable(io.in.bits.uop, io.in.fire())
55  val func = uop.ctrl.fuOpType
56
57  // NOTE: icache & tlb & sbuffer must receive flush signal at any time
58  sbuffer      := state === s_wait && !(func === FenceOpType.sfence && disableSfence)
59  fencei       := state === s_icache
60  sfence.valid := state === s_tlb && !disableSfence
61  sfence.bits.rs1  := uop.ctrl.lsrc(0) === 0.U
62  sfence.bits.rs2  := uop.ctrl.lsrc(1) === 0.U
63  sfence.bits.addr := RegEnable(src1, io.in.fire())
64
65  when (state === s_idle && valid) { state := s_wait }
66  when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache }
67  when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb }
68  when (state === s_wait && func === FenceOpType.fence  && sbEmpty) { state := s_fence }
69  when (state =/= s_idle && state =/= s_wait) { state := s_idle }
70
71  io.in.ready := state === s_idle
72  io.out.valid := state =/= s_idle && state =/= s_wait
73  io.out.bits.data := DontCare
74  io.out.bits.uop := uop
75  io.out.bits.uop.cf.exceptionVec(illegalInstr) := func === FenceOpType.sfence && disableSfence
76
77  XSDebug(valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx}\n")
78  XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n")
79  XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
80
81  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
82  assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true")
83}
84