1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.ExceptionNO.illegalInstr 25 26class FenceToSbuffer extends Bundle { 27 val flushSb = Output(Bool()) 28 val sbIsEmpty = Input(Bool()) 29} 30 31class Fence(implicit p: Parameters) extends FunctionUnit { 32 33 val sfence = IO(Output(new SfenceBundle)) 34 val fencei = IO(Output(Bool())) 35 val toSbuffer = IO(new FenceToSbuffer) 36 val disableSfence = IO(Input(Bool())) 37 38 val (valid, src1) = ( 39 io.in.valid, 40 io.in.bits.src(0) 41 ) 42 43 val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6) 44 45 val state = RegInit(s_idle) 46 /* fsm 47 * s_idle : init state, send sbflush 48 * s_wait : send sbflush, wait for sbEmpty 49 * s_tlb : flush tlb, just hold one cycle 50 * s_icache: flush icache, just hold one cycle 51 * s_fence : do nothing, for timing optimiaztion 52 * s_nofence: do nothing , for Svinval extension 53 */ 54 55 val sbuffer = toSbuffer.flushSb 56 val sbEmpty = toSbuffer.sbIsEmpty 57 val uop = RegEnable(io.in.bits.uop, io.in.fire()) 58 val func = uop.ctrl.fuOpType 59 60 // NOTE: icache & tlb & sbuffer must receive flush signal at any time 61 sbuffer := state === s_wait && !(func === FenceOpType.sfence && disableSfence) 62 fencei := state === s_icache 63 sfence.valid := state === s_tlb && !disableSfence 64 sfence.bits.rs1 := uop.ctrl.imm(4, 0) === 0.U 65 sfence.bits.rs2 := uop.ctrl.imm(9, 5) === 0.U 66 XSError(sfence.valid && uop.ctrl.lsrc(0) =/= uop.ctrl.imm(4, 0), "lsrc0 is passed by imm\n") 67 XSError(sfence.valid && uop.ctrl.lsrc(1) =/= uop.ctrl.imm(9, 5), "lsrc1 is passed by imm\n") 68 sfence.bits.addr := RegEnable(io.in.bits.src(0), io.in.fire()) 69 sfence.bits.asid := RegEnable(io.in.bits.src(1), io.in.fire()) 70 71 when (state === s_idle && io.in.valid) { state := s_wait } 72 when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache } 73 when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb } 74 when (state === s_wait && func === FenceOpType.fence && sbEmpty) { state := s_fence } 75 when (state === s_wait && func === FenceOpType.nofence && sbEmpty) { state := s_nofence } 76 when (state =/= s_idle && state =/= s_wait) { state := s_idle } 77 78 io.in.ready := state === s_idle 79 io.out.valid := state =/= s_idle && state =/= s_wait 80 io.out.bits.data := DontCare 81 io.out.bits.uop := uop 82 io.out.bits.uop.cf.exceptionVec(illegalInstr) := func === FenceOpType.sfence && disableSfence 83 84 XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InrobIdx:${io.in.bits.uop.robIdx}\n") 85 XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n") 86 XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutrobIdx:${io.out.bits.uop.robIdx}\n") 87 88 assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen)) 89 assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true") 90} 91