1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan.ExceptionNO.illegalInstr 24import xiangshan._ 25 26class FenceIO(implicit p: Parameters) extends XSBundle { 27 val sfence = Output(new SfenceBundle) 28 val fencei = Output(Bool()) 29 val sbuffer = new FenceToSbuffer 30 val disableSfence = Input(Bool()) 31} 32 33class FenceToSbuffer extends Bundle { 34 val flushSb = Output(Bool()) 35 val sbIsEmpty = Input(Bool()) 36} 37 38class Fence(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 39 40 val sfence = io.fenceio.get.sfence 41 val fencei = io.fenceio.get.fencei 42 val toSbuffer = io.fenceio.get.sbuffer 43 val disableSfence = io.fenceio.get.disableSfence 44 45 val (valid, src1) = ( 46 io.in.valid, 47 io.in.bits.data.src(0) 48 ) 49 50 val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6) 51 52 val state = RegInit(s_idle) 53 /* fsm 54 * s_idle : init state, send sbflush 55 * s_wait : send sbflush, wait for sbEmpty 56 * s_tlb : flush tlb, just hold one cycle 57 * s_icache: flush icache, just hold one cycle 58 * s_fence : do nothing, for timing optimiaztion 59 * s_nofence: do nothing , for Svinval extension 60 */ 61 62 val sbuffer = toSbuffer.flushSb 63 val sbEmpty = toSbuffer.sbIsEmpty 64 val uop = RegEnable(io.in.bits, io.in.fire) 65 val func = uop.ctrl.fuOpType 66 67 // NOTE: icache & tlb & sbuffer must receive flush signal at any time 68 sbuffer := state === s_wait && !(func === FenceOpType.sfence && disableSfence) 69 fencei := state === s_icache 70 sfence.valid := state === s_tlb && !disableSfence 71 sfence.bits.rs1 := uop.data.imm(4, 0) === 0.U 72 sfence.bits.rs2 := uop.data.imm(9, 5) === 0.U 73 sfence.bits.flushPipe := uop.ctrl.flushPipe.get 74// XSError(sfence.valid && uop.lsrc(0) =/= uop.imm(4, 0), "lsrc0 is passed by imm\n") 75// XSError(sfence.valid && uop.lsrc(1) =/= uop.imm(9, 5), "lsrc1 is passed by imm\n") 76 sfence.bits.addr := RegEnable(io.in.bits.data.src(0), io.in.fire) 77 sfence.bits.asid := RegEnable(io.in.bits.data.src(1), io.in.fire) 78 79 when (state === s_idle && io.in.valid) { state := s_wait } 80 when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache } 81 when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb } 82 when (state === s_wait && func === FenceOpType.fence && sbEmpty) { state := s_fence } 83 when (state === s_wait && func === FenceOpType.nofence && sbEmpty) { state := s_nofence } 84 when (state =/= s_idle && state =/= s_wait) { state := s_idle } 85 86 io.in.ready := state === s_idle 87 io.out.valid := state =/= s_idle && state =/= s_wait 88 io.out.bits.res.data := 0.U 89 io.out.bits.ctrl.robIdx := uop.ctrl.robIdx 90 io.out.bits.res.pc.get := uop.data.pc.get 91 io.out.bits.ctrl.pdest := uop.ctrl.pdest 92 io.out.bits.ctrl.flushPipe.get := uop.ctrl.flushPipe.get 93 io.out.bits.ctrl.exceptionVec.get := 0.U.asTypeOf(io.out.bits.ctrl.exceptionVec.get) 94 io.out.bits.ctrl.exceptionVec.get(illegalInstr) := func === FenceOpType.sfence && disableSfence 95 io.out.bits.perfDebugInfo := io.in.bits.perfDebugInfo 96 97 XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.data.pc.get)} InrobIdx:${io.in.bits.ctrl.robIdx}\n") 98 XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n") 99 XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.res.pc.get)} OutrobIdx:${io.out.bits.ctrl.robIdx}\n") 100 101 assert(!(io.out.valid && io.out.bits.ctrl.rfWen)) 102 assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true") 103} 104