1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24 25class FenceToSbuffer extends Bundle { 26 val flushSb = Output(Bool()) 27 val sbIsEmpty = Input(Bool()) 28} 29 30class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO { 31 32 val sfence = IO(Output(new SfenceBundle)) 33 val fencei = IO(Output(Bool())) 34 val toSbuffer = IO(new FenceToSbuffer) 35 val disableSfence = IO(Input(Bool())) 36 37 val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: Nil = Enum(5) 38 val state = RegInit(s_idle) 39 /* fsm 40 * s_idle : init state, send sbflush 41 * s_wait : send sbflush, wait for sbEmpty 42 * s_tlb : flush tlb, just hold one cycle 43 * s_icache: flush icache, just hold one cycle 44 * s_fence : do nothing, for timing optimiaztion 45 */ 46 47 val sbuffer = toSbuffer.flushSb 48 val sbEmpty = toSbuffer.sbIsEmpty 49 val uop = RegEnable(io.in.bits.uop, io.in.fire()) 50 val func = uop.ctrl.fuOpType 51 52 // NOTE: icache & tlb & sbuffer must receive flush signal at any time 53 sbuffer := state === s_wait && !(func === FenceOpType.sfence && disableSfence) 54 fencei := state === s_icache 55 sfence.valid := state === s_tlb && !disableSfence 56 sfence.bits.rs1 := uop.ctrl.imm(4, 0) === 0.U 57 sfence.bits.rs2 := uop.ctrl.imm(9, 5) === 0.U 58 XSError(sfence.valid && uop.ctrl.lsrc(0) =/= uop.ctrl.imm(4, 0), "lsrc0 is passed by imm\n") 59 XSError(sfence.valid && uop.ctrl.lsrc(1) =/= uop.ctrl.imm(9, 5), "lsrc1 is passed by imm\n") 60 sfence.bits.addr := RegEnable(io.in.bits.src(0), io.in.fire()) 61 sfence.bits.asid := RegEnable(io.in.bits.src(1), io.in.fire()) 62 63 when (state === s_idle && io.in.valid) { state := s_wait } 64 when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache } 65 when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb } 66 when (state === s_wait && func === FenceOpType.fence && sbEmpty) { state := s_fence } 67 when (state =/= s_idle && state =/= s_wait) { state := s_idle } 68 69 io.in.ready := state === s_idle 70 io.out.valid := state =/= s_idle && state =/= s_wait 71 io.out.bits.data := DontCare 72 io.out.bits.uop := uop 73 io.out.bits.uop.cf.exceptionVec(illegalInstr) := func === FenceOpType.sfence && disableSfence 74 75 XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InrobIdx:${io.in.bits.uop.robIdx}\n") 76 XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n") 77 XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutrobIdx:${io.out.bits.uop.robIdx}\n") 78 79 assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen)) 80 assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true") 81} 82