1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan.ExceptionNO.illegalInstr 25import xiangshan._ 26import xiangshan.v2backend.FuConfig 27import xiangshan.v2backend.fu.FuncUnit 28 29class FenceIO(implicit p: Parameters) extends XSBundle { 30 val sfence = Output(new SfenceBundle) 31 val fencei = Output(Bool()) 32 val sbuffer = new FenceToSbuffer 33 val disableSfence = Input(Bool()) 34} 35 36class FenceToSbuffer extends Bundle { 37 val flushSb = Output(Bool()) 38 val sbIsEmpty = Input(Bool()) 39} 40 41class Fence(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 42 43 val sfence = io.fenceio.get.sfence 44 val fencei = io.fenceio.get.fencei 45 val toSbuffer = io.fenceio.get.sbuffer 46 val disableSfence = io.fenceio.get.disableSfence 47 48 val (valid, src1) = ( 49 io.in.valid, 50 io.in.bits.src(0) 51 ) 52 53 val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6) 54 55 val state = RegInit(s_idle) 56 /* fsm 57 * s_idle : init state, send sbflush 58 * s_wait : send sbflush, wait for sbEmpty 59 * s_tlb : flush tlb, just hold one cycle 60 * s_icache: flush icache, just hold one cycle 61 * s_fence : do nothing, for timing optimiaztion 62 * s_nofence: do nothing , for Svinval extension 63 */ 64 65 val sbuffer = toSbuffer.flushSb 66 val sbEmpty = toSbuffer.sbIsEmpty 67 val uop = RegEnable(io.in.bits, io.in.fire) 68 val func = uop.fuOpType 69 70 // NOTE: icache & tlb & sbuffer must receive flush signal at any time 71 sbuffer := state === s_wait && !(func === FenceOpType.sfence && disableSfence) 72 fencei := state === s_icache 73 sfence.valid := state === s_tlb && !disableSfence 74 sfence.bits.rs1 := uop.imm(4, 0) === 0.U 75 sfence.bits.rs2 := uop.imm(9, 5) === 0.U 76 sfence.bits.flushPipe := uop.flushPipe.get 77// XSError(sfence.valid && uop.lsrc(0) =/= uop.imm(4, 0), "lsrc0 is passed by imm\n") 78// XSError(sfence.valid && uop.lsrc(1) =/= uop.imm(9, 5), "lsrc1 is passed by imm\n") 79 sfence.bits.addr := RegEnable(io.in.bits.src(0), io.in.fire()) 80 sfence.bits.asid := RegEnable(io.in.bits.src(1), io.in.fire()) 81 82 when (state === s_idle && io.in.valid) { state := s_wait } 83 when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache } 84 when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb } 85 when (state === s_wait && func === FenceOpType.fence && sbEmpty) { state := s_fence } 86 when (state === s_wait && func === FenceOpType.nofence && sbEmpty) { state := s_nofence } 87 when (state =/= s_idle && state =/= s_wait) { state := s_idle } 88 89 io.in.ready := state === s_idle 90 io.out.valid := state =/= s_idle && state =/= s_wait 91 io.out.bits.data := 0.U 92 io.out.bits.robIdx := uop.robIdx 93 io.out.bits.pc.get := uop.pc.get 94 io.out.bits.pdest := uop.pdest 95 io.out.bits.flushPipe.get := uop.flushPipe.get 96 io.out.bits.exceptionVec.get := 0.U.asTypeOf(io.out.bits.exceptionVec.get) 97 io.out.bits.exceptionVec.get(illegalInstr) := func === FenceOpType.sfence && disableSfence 98 99 XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.pc.get)} InrobIdx:${io.in.bits.robIdx}\n") 100 XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n") 101 XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.pc.get)} OutrobIdx:${io.out.bits.robIdx}\n") 102 103 // assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen)) 104 assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true") 105} 106