1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.{LookupTree, LookupTreeDefault, ParallelMux, SignExt, ZeroExt} 23import xiangshan._ 24 25class VsetModule(implicit p: Parameters) extends XSModule { 26 val io = IO(new Bundle() { 27 val lsrc0NotZero = Input(Bool()) 28 val ldest = Input(UInt(6.W)) 29 val src0 = Input(UInt(XLEN.W)) 30 val src1 = Input(UInt(XLEN.W)) 31 val func = Input(FuOpType()) 32 val vconfig = Input(UInt(16.W)) 33 34 val res = Output(UInt(XLEN.W)) 35 }) 36 val vtype = io.src1(7, 0) 37 val vlmul = vtype(2, 0) 38 val vsew = vtype(5, 3) 39 40 val avlImm = Cat(0.U(3.W), io.src1(14, 10)) 41 val vlLast = io.vconfig(15, 8) 42 43 val rd = io.ldest 44 val lsrc0NotZero = io.lsrc0NotZero 45 val vl = WireInit(0.U(XLEN.W)) 46 val vconfig = WireInit(0.U(XLEN.W)) 47 48 // vlen = 128 49 val vlmaxVec = (0 to 7).map(i => if(i < 4) (16 << i).U(8.W) else (16 >> (8 - i)).U(8.W)) 50 val shamt = vlmul + (~vsew).asUInt + 1.U 51 val vlmax = ParallelMux((0 to 7).map(_.U).map(_ === shamt), vlmaxVec) 52 53 val isVsetivli = io.func === ALUOpType.vsetivli2 || io.func === ALUOpType.vsetivli1 54 val vlWhenRs1Not0 = Mux(isVsetivli, Mux(avlImm > vlmax, vlmax, avlImm), 55 Mux(io.src0 > vlmax, vlmax, io.src0)) 56 vl := Mux(isVsetivli, Mux(avlImm > vlmax, vlmax, avlImm), 57 Mux(lsrc0NotZero, Mux(io.src0 > vlmax, vlmax, io.src0), 58 Mux(rd === 0.U, Cat(0.U(56.W), vlLast), vlmax))) 59 60 vconfig := Cat(0.U(48.W), vl(7, 0), vtype) 61 62 io.res := Mux(io.func === ALUOpType.vsetvli2 || io.func === ALUOpType.vsetvl2 || io.func === ALUOpType.vsetivli2, vl, vconfig) 63} 64 65class AddModule(implicit p: Parameters) extends XSModule { 66 val io = IO(new Bundle() { 67 val src = Vec(2, Input(UInt(XLEN.W))) 68 val srcw = Input(UInt((XLEN/2).W)) 69 val add = Output(UInt(XLEN.W)) 70 val addw = Output(UInt((XLEN/2).W)) 71 }) 72 io.add := io.src(0) + io.src(1) 73 // TODO: why this extra adder? 74 io.addw := io.srcw + io.src(1)(31,0) 75} 76 77class SubModule(implicit p: Parameters) extends XSModule { 78 val io = IO(new Bundle() { 79 val src = Vec(2, Input(UInt(XLEN.W))) 80 val sub = Output(UInt((XLEN+1).W)) 81 }) 82 io.sub := (io.src(0) +& (~io.src(1)).asUInt()) + 1.U 83} 84 85class LeftShiftModule(implicit p: Parameters) extends XSModule { 86 val io = IO(new Bundle() { 87 val shamt = Input(UInt(6.W)) 88 val revShamt = Input(UInt(6.W)) 89 val sllSrc = Input(UInt(XLEN.W)) 90 val sll = Output(UInt(XLEN.W)) 91 val revSll = Output(UInt(XLEN.W)) 92 }) 93 io.sll := io.sllSrc << io.shamt 94 io.revSll := io.sllSrc << io.revShamt 95} 96 97class LeftShiftWordModule(implicit p: Parameters) extends XSModule { 98 val io = IO(new Bundle() { 99 val shamt = Input(UInt(5.W)) 100 val revShamt = Input(UInt(5.W)) 101 val sllSrc = Input(UInt((XLEN/2).W)) 102 val sllw = Output(UInt((XLEN/2).W)) 103 val revSllw = Output(UInt((XLEN/2).W)) 104 }) 105 io.sllw := io.sllSrc << io.shamt 106 io.revSllw := io.sllSrc << io.revShamt 107} 108 109class RightShiftModule(implicit p: Parameters) extends XSModule { 110 val io = IO(new Bundle() { 111 val shamt = Input(UInt(6.W)) 112 val revShamt = Input(UInt(6.W)) 113 val srlSrc, sraSrc = Input(UInt(XLEN.W)) 114 val srl, sra = Output(UInt(XLEN.W)) 115 val revSrl = Output(UInt(XLEN.W)) 116 }) 117 io.srl := io.srlSrc >> io.shamt 118 io.sra := (io.sraSrc.asSInt() >> io.shamt).asUInt() 119 io.revSrl := io.srlSrc >> io.revShamt 120} 121 122class RightShiftWordModule(implicit p: Parameters) extends XSModule { 123 val io = IO(new Bundle() { 124 val shamt = Input(UInt(5.W)) 125 val revShamt = Input(UInt(5.W)) 126 val srlSrc, sraSrc = Input(UInt((XLEN/2).W)) 127 val srlw, sraw = Output(UInt((XLEN/2).W)) 128 val revSrlw = Output(UInt((XLEN/2).W)) 129 }) 130 131 io.srlw := io.srlSrc >> io.shamt 132 io.sraw := (io.sraSrc.asSInt() >> io.shamt).asUInt() 133 io.revSrlw := io.srlSrc >> io.revShamt 134} 135 136 137class MiscResultSelect(implicit p: Parameters) extends XSModule { 138 val io = IO(new Bundle() { 139 val func = Input(UInt(6.W)) 140 val and, or, xor, orcb, orh48, sextb, packh, sexth, packw, revb, rev8, pack = Input(UInt(XLEN.W)) 141 val src = Input(UInt(XLEN.W)) 142 val miscRes = Output(UInt(XLEN.W)) 143 }) 144 145 val logicRes = VecInit(Seq( 146 io.and, 147 io.or, 148 io.xor, 149 io.orcb 150 ))(io.func(2, 1)) 151 val miscRes = VecInit(Seq(io.sextb, io.packh, io.sexth, io.packw))(io.func(1, 0)) 152 val logicBase = Mux(io.func(3), miscRes, logicRes) 153 154 val revRes = VecInit(Seq(io.revb, io.rev8, io.pack, io.orh48))(io.func(1, 0)) 155 val customRes = VecInit(Seq( 156 Cat(0.U(31.W), io.src(31, 0), 0.U(1.W)), 157 Cat(0.U(30.W), io.src(31, 0), 0.U(2.W)), 158 Cat(0.U(29.W), io.src(31, 0), 0.U(3.W)), 159 Cat(0.U(56.W), io.src(15, 8))))(io.func(1, 0)) 160 val logicAdv = Mux(io.func(3), customRes, revRes) 161 162 val mask = Cat(Fill(15, io.func(0)), 1.U(1.W)) 163 val maskedLogicRes = mask & logicRes 164 165 io.miscRes := Mux(io.func(5), maskedLogicRes, Mux(io.func(4), logicAdv, logicBase)) 166} 167 168class ShiftResultSelect(implicit p: Parameters) extends XSModule { 169 val io = IO(new Bundle() { 170 val func = Input(UInt(4.W)) 171 val sll, srl, sra, rol, ror, bclr, bset, binv, bext = Input(UInt(XLEN.W)) 172 val shiftRes = Output(UInt(XLEN.W)) 173 }) 174 175 // val leftBit = Mux(io.func(1), io.binv, Mux(io.func(0), io.bset, io.bclr)) 176 // val leftRes = Mux(io.func(2), leftBit, io.sll) 177 // val rightRes = Mux(io.func(1) && io.func(0), io.sra, Mux(io.func(1), io.bext, io.srl)) 178 val resultSource = VecInit(Seq( 179 io.sll, 180 io.sll, 181 io.bclr, 182 io.bset, 183 io.binv, 184 io.srl, 185 io.bext, 186 io.sra 187 )) 188 val simple = resultSource(io.func(2, 0)) 189 190 io.shiftRes := Mux(io.func(3), Mux(io.func(1), io.ror, io.rol), simple) 191} 192 193class WordResultSelect(implicit p: Parameters) extends XSModule { 194 val io = IO(new Bundle() { 195 val func = Input(UInt()) 196 val sllw, srlw, sraw, rolw, rorw, addw, subw = Input(UInt((XLEN/2).W)) 197 val wordRes = Output(UInt(XLEN.W)) 198 }) 199 200 val addsubRes = Mux(!io.func(2) && io.func(1), io.subw, io.addw) 201 val shiftRes = Mux(io.func(2), Mux(io.func(0), io.rorw, io.rolw), 202 Mux(io.func(1), io.sraw, Mux(io.func(0), io.srlw, io.sllw))) 203 val wordRes = Mux(io.func(3), shiftRes, addsubRes) 204 io.wordRes := SignExt(wordRes, XLEN) 205} 206 207 208class AluResSel(implicit p: Parameters) extends XSModule { 209 val io = IO(new Bundle() { 210 val func = Input(UInt(4.W)) 211 val addRes, shiftRes, miscRes, compareRes, wordRes, vsetRes = Input(UInt(XLEN.W)) 212 val aluRes = Output(UInt(XLEN.W)) 213 }) 214 215 val res = Mux(io.func(3), io.vsetRes, 216 Mux(io.func(2, 1) === 0.U, Mux(io.func(0), io.wordRes, io.shiftRes), 217 Mux(!io.func(2), Mux(io.func(0), io.compareRes, io.addRes), io.miscRes))) 218 io.aluRes := res 219} 220 221class AluDataModule(implicit p: Parameters) extends XSModule { 222 val io = IO(new Bundle() { 223 val src = Vec(2, Input(UInt(XLEN.W))) 224 val func = Input(FuOpType()) 225 val result = Output(UInt(XLEN.W)) 226 val lsrc0NotZero = Input(Bool()) 227 val ldest = Input(UInt(6.W)) 228 val vconfig = Input(UInt(16.W)) 229 }) 230 val (src1, src2, func) = (io.src(0), io.src(1), io.func) 231 232 val shamt = src2(5, 0) 233 val revShamt = ~src2(5,0) + 1.U 234 235 // slliuw, sll 236 val leftShiftModule = Module(new LeftShiftModule) 237 val sll = leftShiftModule.io.sll 238 val revSll = leftShiftModule.io.revSll 239 leftShiftModule.io.sllSrc := Cat(Fill(32, func(0)), Fill(32, 1.U)) & src1 240 leftShiftModule.io.shamt := shamt 241 leftShiftModule.io.revShamt := revShamt 242 243 // bclr, bset, binv 244 val bitShift = 1.U << src2(5, 0) 245 val bclr = src1 & ~bitShift 246 val bset = src1 | bitShift 247 val binv = src1 ^ bitShift 248 249 // srl, sra, bext 250 val rightShiftModule = Module(new RightShiftModule) 251 val srl = rightShiftModule.io.srl 252 val revSrl = rightShiftModule.io.revSrl 253 val sra = rightShiftModule.io.sra 254 rightShiftModule.io.shamt := shamt 255 rightShiftModule.io.revShamt := revShamt 256 rightShiftModule.io.srlSrc := src1 257 rightShiftModule.io.sraSrc := src1 258 val bext = srl(0) 259 260 val rol = revSrl | sll 261 val ror = srl | revSll 262 263 // vset 264 val vsetModule = Module(new VsetModule) 265 vsetModule.io.lsrc0NotZero := io.lsrc0NotZero 266 vsetModule.io.ldest := io.ldest 267 vsetModule.io.src0 := io.src(0) 268 vsetModule.io.src1 := io.src(1) 269 vsetModule.io.func := io.func 270 vsetModule.io.vconfig := io.vconfig 271 272 // addw 273 val addModule = Module(new AddModule) 274 addModule.io.srcw := Mux(!func(2) && func(0), ZeroExt(src1(0), XLEN), src1(31, 0)) 275 val addwResultAll = VecInit(Seq( 276 ZeroExt(addModule.io.addw(0), XLEN), 277 ZeroExt(addModule.io.addw(7, 0), XLEN), 278 ZeroExt(addModule.io.addw(15, 0), XLEN), 279 SignExt(addModule.io.addw(15, 0), XLEN) 280 )) 281 val addw = Mux(func(2), addwResultAll(func(1, 0)), addModule.io.addw) 282 283 // subw 284 val subModule = Module(new SubModule) 285 val subw = subModule.io.sub 286 287 // sllw 288 val leftShiftWordModule = Module(new LeftShiftWordModule) 289 val sllw = leftShiftWordModule.io.sllw 290 val revSllw = leftShiftWordModule.io.revSllw 291 leftShiftWordModule.io.sllSrc := src1 292 leftShiftWordModule.io.shamt := shamt 293 leftShiftWordModule.io.revShamt := revShamt 294 295 val rightShiftWordModule = Module(new RightShiftWordModule) 296 val srlw = rightShiftWordModule.io.srlw 297 val revSrlw = rightShiftWordModule.io.revSrlw 298 val sraw = rightShiftWordModule.io.sraw 299 rightShiftWordModule.io.shamt := shamt 300 rightShiftWordModule.io.revShamt := revShamt 301 rightShiftWordModule.io.srlSrc := src1 302 rightShiftWordModule.io.sraSrc := src1 303 304 val rolw = revSrlw | sllw 305 val rorw = srlw | revSllw 306 307 // add 308 val wordMaskAddSource = Cat(Fill(32, func(0)), Fill(32, 1.U)) & src1 309 val shaddSource = VecInit(Seq( 310 Cat(wordMaskAddSource(62, 0), 0.U(1.W)), 311 Cat(wordMaskAddSource(61, 0), 0.U(2.W)), 312 Cat(wordMaskAddSource(60, 0), 0.U(3.W)), 313 Cat(wordMaskAddSource(59, 0), 0.U(4.W)) 314 )) 315 val sraddSource = VecInit(Seq( 316 ZeroExt(src1(63, 29), XLEN), 317 ZeroExt(src1(63, 30), XLEN), 318 ZeroExt(src1(63, 31), XLEN), 319 ZeroExt(src1(63, 32), XLEN) 320 )) 321 // TODO: use decoder or other libraries to optimize timing 322 // Now we assume shadd has the worst timing. 323 addModule.io.src(0) := Mux(func(3), shaddSource(func(2, 1)), 324 Mux(func(2), sraddSource(func(1, 0)), 325 Mux(func(1), ZeroExt(src1(0), XLEN), wordMaskAddSource)) 326 ) 327 addModule.io.src(1) := src2 328 val add = addModule.io.add 329 330 // sub 331 val sub = subModule.io.sub 332 subModule.io.src(0) := src1 333 subModule.io.src(1) := src2 334 val sltu = !sub(XLEN) 335 val slt = src1(XLEN - 1) ^ src2(XLEN - 1) ^ sltu 336 val maxMin = Mux(slt ^ func(0), src2, src1) 337 val maxMinU = Mux(sltu ^ func(0), src2, src1) 338 val compareRes = Mux(func(2), Mux(func(1), maxMin, maxMinU), Mux(func(1), slt, Mux(func(0), sltu, sub))) 339 340 // logic 341 val logicSrc2 = Mux(!func(5) && func(0), ~src2, src2) 342 val and = src1 & logicSrc2 343 val or = src1 | logicSrc2 344 val xor = src1 ^ logicSrc2 345 val orcb = Cat((0 until 8).map(i => Fill(8, src1(i * 8 + 7, i * 8).orR)).reverse) 346 val orh48 = Cat(src1(63, 8), 0.U(8.W)) | src2 347 348 val sextb = SignExt(src1(7, 0), XLEN) 349 val packh = Cat(src2(7,0), src1(7,0)) 350 val sexth = SignExt(src1(15, 0), XLEN) 351 val packw = SignExt(Cat(src2(15, 0), src1(15, 0)), XLEN) 352 353 val revb = Cat((0 until 8).map(i => Reverse(src1(8 * i + 7, 8 * i))).reverse) 354 val pack = Cat(src2(31, 0), src1(31, 0)) 355 val rev8 = Cat((0 until 8).map(i => src1(8 * i + 7, 8 * i))) 356 357 358 // Result Select 359 val shiftResSel = Module(new ShiftResultSelect) 360 shiftResSel.io.func := func(3, 0) 361 shiftResSel.io.sll := sll 362 shiftResSel.io.srl := srl 363 shiftResSel.io.sra := sra 364 shiftResSel.io.rol := rol 365 shiftResSel.io.ror := ror 366 shiftResSel.io.bclr := bclr 367 shiftResSel.io.binv := binv 368 shiftResSel.io.bset := bset 369 shiftResSel.io.bext := bext 370 val shiftRes = shiftResSel.io.shiftRes 371 372 val miscResSel = Module(new MiscResultSelect) 373 miscResSel.io.func := func(5, 0) 374 miscResSel.io.and := and 375 miscResSel.io.or := or 376 miscResSel.io.xor := xor 377 miscResSel.io.orcb := orcb 378 miscResSel.io.orh48 := orh48 379 miscResSel.io.sextb := sextb 380 miscResSel.io.packh := packh 381 miscResSel.io.sexth := sexth 382 miscResSel.io.packw := packw 383 miscResSel.io.revb := revb 384 miscResSel.io.rev8 := rev8 385 miscResSel.io.pack := pack 386 miscResSel.io.src := src1 387 val miscRes = miscResSel.io.miscRes 388 389 val wordResSel = Module(new WordResultSelect) 390 wordResSel.io.func := func 391 wordResSel.io.addw := addw 392 wordResSel.io.subw := subw 393 wordResSel.io.sllw := sllw 394 wordResSel.io.srlw := srlw 395 wordResSel.io.sraw := sraw 396 wordResSel.io.rolw := rolw 397 wordResSel.io.rorw := rorw 398 val wordRes = wordResSel.io.wordRes 399 400 val aluResSel = Module(new AluResSel) 401 aluResSel.io.func := func(7, 4) 402 aluResSel.io.addRes := add 403 aluResSel.io.compareRes := compareRes 404 aluResSel.io.shiftRes := shiftRes 405 aluResSel.io.miscRes := miscRes 406 aluResSel.io.wordRes := wordRes 407 aluResSel.io.vsetRes := vsetModule.io.res 408 val aluRes = aluResSel.io.aluRes 409 410 io.result := aluRes 411} 412 413class Alu(implicit p: Parameters) extends FUWithRedirect { 414 415 val uop = io.in.bits.uop 416 417 val dataModule = Module(new AluDataModule) 418 val bru = Module(new Branch()(p)) 419 420 bru.io.in <> io.in 421 bru.io.in.bits.uop <> io.in.bits.uop 422 bru.io.redirectIn <> io.redirectIn 423 bru.io.out.ready := io.out.ready 424 425 dataModule.io.src := io.in.bits.src.take(2) 426 dataModule.io.func := io.in.bits.uop.ctrl.fuOpType 427 dataModule.io.lsrc0NotZero := uop.ctrl.imm(15) // lsrc(0) Not Zero 428 dataModule.io.ldest := uop.ctrl.ldest 429 dataModule.io.vconfig := uop.ctrl.vconfig 430 431 redirectOutValid := bru.redirectOutValid 432 redirectOut <> bru.redirectOut 433 434 io.in.ready := io.out.ready 435 io.out.valid := io.in.valid 436 io.out.bits.uop <> io.in.bits.uop 437 io.out.bits.data := dataModule.io.result 438} 439