1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import utils.{LookupTree, LookupTreeDefault, SignExt, XSDebug, ZeroExt} 6import xiangshan._ 7import xiangshan.backend.ALUOpType 8 9class Alu extends FunctionUnit with HasRedirectOut { 10 11 val (src1, src2, offset, func, pc, uop) = ( 12 io.in.bits.src(0), 13 io.in.bits.src(1), 14 io.in.bits.uop.ctrl.imm, 15 io.in.bits.uop.ctrl.fuOpType, 16 SignExt(io.in.bits.uop.cf.pc, AddrBits), 17 io.in.bits.uop 18 ) 19 20 val valid = io.in.valid 21 22 val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw) 23 val adderRes = (src1 +& (src2 ^ Fill(XLEN, isAdderSub))) + isAdderSub 24 val xorRes = src1 ^ src2 25 val sltu = !adderRes(XLEN) 26 val slt = xorRes(XLEN-1) ^ sltu 27 28 val shsrc1 = LookupTreeDefault(func, src1, List( 29 ALUOpType.srlw -> ZeroExt(src1(31,0), 64), 30 ALUOpType.sraw -> SignExt(src1(31,0), 64) 31 )) 32 val shamt = Mux(ALUOpType.isWordOp(func), src2(4, 0), src2(5, 0)) 33 val res = LookupTreeDefault(func(3, 0), adderRes, List( 34 ALUOpType.sll -> ((shsrc1 << shamt)(XLEN-1, 0)), 35 ALUOpType.slt -> ZeroExt(slt, XLEN), 36 ALUOpType.sltu -> ZeroExt(sltu, XLEN), 37 ALUOpType.xor -> xorRes, 38 ALUOpType.srl -> (shsrc1 >> shamt), 39 ALUOpType.or -> (src1 | src2), 40 ALUOpType.and -> (src1 & src2), 41 ALUOpType.sra -> ((shsrc1.asSInt >> shamt).asUInt) 42 )) 43 val aluRes = Mux(ALUOpType.isWordOp(func), SignExt(res(31,0), 64), res) 44 45 val branchOpTable = List( 46 ALUOpType.getBranchType(ALUOpType.beq) -> !xorRes.orR, 47 ALUOpType.getBranchType(ALUOpType.blt) -> slt, 48 ALUOpType.getBranchType(ALUOpType.bltu) -> sltu 49 ) 50 51 val isBranch = uop.cf.brUpdate.pd.isBr// ALUOpType.isBranch(func) 52 val isRVC = uop.cf.brUpdate.pd.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U) 53 val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func) 54 val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0) 55 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 56 57 redirectOutValid := io.out.valid && isBranch 58 redirectOut.pc := uop.cf.pc 59 redirectOut.target := Mux(!taken && isBranch, snpc, target) 60 redirectOut.brTag := uop.brTag 61 redirectOut.level := RedirectLevel.flushAfter 62 redirectOut.interrupt := DontCare 63 redirectOut.roqIdx := uop.roqIdx 64 65 brUpdate := uop.cf.brUpdate 66 // override brUpdate 67 brUpdate.pc := uop.cf.pc 68 brUpdate.target := Mux(!taken && isBranch, snpc, target) 69 brUpdate.brTarget := target 70 brUpdate.taken := isBranch && taken 71 brUpdate.brTag := uop.brTag 72 73 io.in.ready := io.out.ready 74 io.out.valid := valid 75 io.out.bits.uop <> io.in.bits.uop 76 io.out.bits.data := aluRes 77} 78