1//package xiangshan.backend.fu 2// 3//import chisel3._ 4//import chisel3.util._ 5//import xiangshan._ 6//import utils._ 7//import xiangshan.backend._ 8// 9//import xiangshan.backend.fu.FunctionUnit._ 10// 11//class Alu extends FunctionUnit(aluCfg) { 12// val io = IO(new ExuIO) 13// 14// 15// override def toString: String = "Alu" 16// 17// val (iovalid, src1, src2, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, 18// io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 19// 20// val redirectHit = uop.brTag.needFlush(io.redirect) 21// val valid = iovalid && !redirectHit 22// 23// val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw) && !ALUOpType.isJump(func) 24// val adderRes = (src1 +& (src2 ^ Fill(XLEN, isAdderSub))) + isAdderSub 25// val xorRes = src1 ^ src2 26// val sltu = !adderRes(XLEN) 27// val slt = xorRes(XLEN-1) ^ sltu 28// 29// val shsrc1 = LookupTreeDefault(func, src1, List( 30// ALUOpType.srlw -> ZeroExt(src1(31,0), 64), 31// ALUOpType.sraw -> SignExt(src1(31,0), 64) 32// )) 33// val shamt = Mux(ALUOpType.isWordOp(func), src2(4, 0), src2(5, 0)) 34// val res = LookupTreeDefault(func(3, 0), adderRes, List( 35// ALUOpType.sll -> ((shsrc1 << shamt)(XLEN-1, 0)), 36// ALUOpType.slt -> ZeroExt(slt, XLEN), 37// ALUOpType.sltu -> ZeroExt(sltu, XLEN), 38// ALUOpType.xor -> xorRes, 39// ALUOpType.srl -> (shsrc1 >> shamt), 40// ALUOpType.or -> (src1 | src2), 41// ALUOpType.and -> (src1 & src2), 42// ALUOpType.sra -> ((shsrc1.asSInt >> shamt).asUInt) 43// )) 44// val aluRes = Mux(ALUOpType.isWordOp(func), SignExt(res(31,0), 64), res) 45// 46// val branchOpTable = List( 47// ALUOpType.getBranchType(ALUOpType.beq) -> !xorRes.orR, 48// ALUOpType.getBranchType(ALUOpType.blt) -> slt, 49// ALUOpType.getBranchType(ALUOpType.bltu) -> sltu 50// ) 51// 52// val isBru = ALUOpType.isBru(func) 53// // val isBranch = io.in.bits.uop.cf.isBr// ALUOpType.isBranch(func) 54// val isBranch = ALUOpType.isBranch(func) 55// val isJump = ALUOpType.isJump(func) 56// val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func) 57// val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0) 58// val isRVC = uop.cf.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U) 59// 60// io.in.ready := io.out.ready 61// val pcLatchSlot = Mux(isRVC, pc + 2.U, pc + 4.U) 62// io.out.bits.redirectValid := io.out.valid && isBru//isBranch 63// io.out.bits.redirect.target := Mux(!taken && isBranch, pcLatchSlot, target) 64// io.out.bits.redirect.brTag := uop.brTag 65// io.out.bits.redirect.isException := DontCare // false.B 66// io.out.bits.redirect.roqIdx := uop.roqIdx 67// 68// io.out.valid := valid 69// io.out.bits.uop <> io.in.bits.uop 70// io.out.bits.data := Mux(isJump, pcLatchSlot, aluRes) 71// 72// XSDebug(io.in.valid, 73// "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:f:%d v:%d\n", 74// io.in.valid, 75// io.in.ready, 76// io.out.valid, 77// io.out.ready, 78// io.redirect.valid, 79// io.redirect.bits.isException, 80// redirectHit, 81// io.redirect.bits.brTag.flag, 82// io.redirect.bits.brTag.value 83// ) 84// XSDebug(io.in.valid, "src1:%x src2:%x offset:%x func:%b pc:%x\n", 85// src1, src2, offset, func, pc) 86// XSDebug(io.out.valid, "res:%x aluRes:%x isRVC:%d isBru:%d isBranch:%d isJump:%d target:%x taken:%d\n", 87// io.out.bits.data, aluRes, isRVC, isBru, isBranch, isJump, target, taken) 88//} 89