xref: /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala (revision b6279fc62b995344eb1f409e6a3b794762f82d5e) 
1package xiangshan.backend.exu
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import xiangshan.backend.fu.{CSRFileIO, FenceIO}
8import xiangshan.backend.Bundles._
9import xiangshan.backend.issue.SchdBlockParams
10import xiangshan.{HasXSParameter, Redirect, XSBundle}
11import utils._
12import xiangshan.backend.fu.FuConfig.{AluCfg, BrhCfg}
13
14class ExuBlock(params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
15  override def shouldBeInlined: Boolean = false
16
17  val exus: Seq[ExeUnit] = params.issueBlockParams.flatMap(_.exuBlockParams.map(x => LazyModule(x.genExuModule)))
18
19  lazy val module = new ExuBlockImp(this)(p, params)
20}
21
22class ExuBlockImp(
23  override val wrapper: ExuBlock
24)(implicit
25  p: Parameters,
26  params: SchdBlockParams
27) extends LazyModuleImp(wrapper) {
28  val io = IO(new ExuBlockIO)
29
30  private val exus = wrapper.exus.map(_.module)
31
32  private val ins: collection.IndexedSeq[DecoupledIO[ExuInput]] = io.in.flatten
33  private val outs: collection.IndexedSeq[DecoupledIO[ExuOutput]] = io.out.flatten
34
35  (ins zip exus zip outs).foreach { case ((input, exu), output) =>
36    exu.io.flush <> io.flush
37    exu.io.csrio.foreach(exuio => io.csrio.get <> exuio)
38    exu.io.fenceio.foreach(exuio => io.fenceio.get <> exuio)
39    exu.io.frm.foreach(exuio => io.frm.get <> exuio)
40    exu.io.vxrm.foreach(exuio => io.vxrm.get <> exuio)
41    exu.io.vlIsZero.foreach(exuio => io.vlIsZero.get := exuio)
42    exu.io.vlIsVlmax.foreach(exuio => io.vlIsVlmax.get := exuio)
43    exu.io.in <> input
44    output <> exu.io.out
45    if (exu.wrapper.exuParams.fuConfigs.contains(AluCfg) || exu.wrapper.exuParams.fuConfigs.contains(BrhCfg)){
46      XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
47    }
48  }
49  val aluFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(AluCfg)).map(_.io.in.fire)
50  for (i <- 0 until (aluFireSeq.size + 1)){
51    XSPerfAccumulate(s"alu_fire_${i}_cnt", PopCount(aluFireSeq) === i.U)
52  }
53  val brhFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(BrhCfg)).map(_.io.in.fire)
54  for (i <- 0 until (brhFireSeq.size + 1)) {
55    XSPerfAccumulate(s"brh_fire_${i}_cnt", PopCount(brhFireSeq) === i.U)
56  }
57}
58
59class ExuBlockIO(implicit p: Parameters, params: SchdBlockParams) extends XSBundle {
60  val flush = Flipped(ValidIO(new Redirect))
61  // in(i)(j): issueblock(i), exu(j)
62  val in: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(params.genExuInputBundle)
63  // out(i)(j): issueblock(i), exu(j).
64  val out: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = params.genExuOutputDecoupledBundle
65
66  val csrio = if (params.hasCSR) Some(new CSRFileIO) else None
67  val fenceio = if (params.hasFence) Some(new FenceIO) else None
68  val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None
69  val vxrm = if (params.needSrcVxrm) Some(Input(UInt(2.W))) else None
70  val vlIsZero = OptionWrapper(params.writeVConfig, Output(Bool()))
71  val vlIsVlmax = OptionWrapper(params.writeVConfig, Output(Bool()))
72}