xref: /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala (revision 7e4f0b19d795b83ff96f23960b1d17200cca3579) 
1package xiangshan.backend.exu
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import xiangshan.backend.fu.{CSRFileIO, FenceIO}
8import xiangshan.backend.Bundles._
9import xiangshan.backend.issue.SchdBlockParams
10import xiangshan.{HasXSParameter, Redirect, XSBundle}
11import utils._
12import xiangshan.backend.fu.FuConfig.{AluCfg, BrhCfg}
13import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm}
14import xiangshan.backend.fu.fpu.Bundles.Frm
15
16class ExuBlock(params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
17  override def shouldBeInlined: Boolean = false
18
19  val exus: Seq[ExeUnit] = params.issueBlockParams.flatMap(_.exuBlockParams.map(x => LazyModule(x.genExuModule)))
20
21  lazy val module = new ExuBlockImp(this)(p, params)
22}
23
24class ExuBlockImp(
25  override val wrapper: ExuBlock
26)(implicit
27  p: Parameters,
28  params: SchdBlockParams
29) extends LazyModuleImp(wrapper) {
30  val io = IO(new ExuBlockIO)
31
32  private val exus = wrapper.exus.map(_.module)
33
34  private val ins: collection.IndexedSeq[DecoupledIO[ExuInput]] = io.in.flatten
35  private val outs: collection.IndexedSeq[DecoupledIO[ExuOutput]] = io.out.flatten
36
37  (ins zip exus zip outs).foreach { case ((input, exu), output) =>
38    exu.io.flush <> io.flush
39    exu.io.csrio.foreach(exuio => io.csrio.get <> exuio)
40    exu.io.fenceio.foreach(exuio => io.fenceio.get <> exuio)
41    exu.io.frm.foreach(exuio => exuio := RegNext(io.frm.get))  // each vf exu pipe frm from csr
42    exu.io.vxrm.foreach(exuio => io.vxrm.get <> exuio)
43    exu.io.vtype.foreach(exuio => io.vtype.get := exuio)
44    exu.io.in <> input
45    output <> exu.io.out
46//    if (exu.wrapper.exuParams.fuConfigs.contains(AluCfg) || exu.wrapper.exuParams.fuConfigs.contains(BrhCfg)){
47//      XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
48//    }
49    XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
50  }
51  val aluFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(AluCfg)).map(_.io.in.fire)
52  for (i <- 0 until (aluFireSeq.size + 1)){
53    XSPerfAccumulate(s"alu_fire_${i}_cnt", PopCount(aluFireSeq) === i.U)
54  }
55  val brhFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(BrhCfg)).map(_.io.in.fire)
56  for (i <- 0 until (brhFireSeq.size + 1)) {
57    XSPerfAccumulate(s"brh_fire_${i}_cnt", PopCount(brhFireSeq) === i.U)
58  }
59}
60
61class ExuBlockIO(implicit p: Parameters, params: SchdBlockParams) extends XSBundle {
62  val flush = Flipped(ValidIO(new Redirect))
63  // in(i)(j): issueblock(i), exu(j)
64  val in: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(params.genExuInputBundle)
65  // out(i)(j): issueblock(i), exu(j).
66  val out: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = params.genExuOutputDecoupledBundle
67
68  val csrio = OptionWrapper(params.hasCSR, new CSRFileIO)
69  val fenceio = OptionWrapper(params.hasFence, new FenceIO)
70  val frm = OptionWrapper(params.needSrcFrm, Input(Frm()))
71  val vxrm = OptionWrapper(params.needSrcVxrm, Input(Vxrm()))
72  val vtype = OptionWrapper(params.writeVType, new VType)
73}