xref: /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala (revision 25dc4a827ee27e3ccbaf02e8e5134872cba28fcd) 
1package xiangshan.backend.exu
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import xiangshan.backend.fu.{CSRFileIO, FenceIO}
8import xiangshan.backend.Bundles._
9import xiangshan.backend.issue.SchdBlockParams
10import xiangshan.{HasXSParameter, Redirect, XSBundle}
11import utility._
12import xiangshan.backend.fu.FuConfig.{AluCfg, BrhCfg}
13import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm}
14import xiangshan.backend.fu.fpu.Bundles.Frm
15import xiangshan.backend.fu.wrapper.CSRInput
16
17class ExuBlock(params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
18  override def shouldBeInlined: Boolean = false
19
20  val exus: Seq[ExeUnit] = params.issueBlockParams.flatMap(_.exuBlockParams.map(x => LazyModule(x.genExuModule)))
21
22  lazy val module = new ExuBlockImp(this)(p, params)
23}
24
25class ExuBlockImp(
26  override val wrapper: ExuBlock
27)(implicit
28  p: Parameters,
29  params: SchdBlockParams
30) extends LazyModuleImp(wrapper) {
31  val io = IO(new ExuBlockIO)
32
33  private val exus = wrapper.exus.map(_.module)
34
35  private val ins: collection.IndexedSeq[DecoupledIO[ExuInput]] = io.in.flatten
36  private val outs: collection.IndexedSeq[DecoupledIO[ExuOutput]] = io.out.flatten
37
38  (ins zip exus zip outs).foreach { case ((input, exu), output) =>
39    exu.io.flush <> io.flush
40    exu.io.csrio.foreach(exuio => io.csrio.get <> exuio)
41    exu.io.csrin.foreach(exuio => io.csrin.get <> exuio)
42    exu.io.fenceio.foreach(exuio => io.fenceio.get <> exuio)
43    exu.io.frm.foreach(exuio => exuio := RegNext(io.frm.get))  // each vf exu pipe frm from csr
44    exu.io.vxrm.foreach(exuio => io.vxrm.get <> exuio)
45    exu.io.vlIsZero.foreach(exuio => io.vlIsZero.get := exuio)
46    exu.io.vlIsVlmax.foreach(exuio => io.vlIsVlmax.get := exuio)
47    exu.io.vtype.foreach(exuio => io.vtype.get := exuio)
48    exu.io.in <> input
49    output <> exu.io.out
50//    if (exu.wrapper.exuParams.fuConfigs.contains(AluCfg) || exu.wrapper.exuParams.fuConfigs.contains(BrhCfg)){
51//      XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
52//    }
53    XSPerfAccumulate(s"${(exu.wrapper.exuParams.name)}_fire_cnt", PopCount(exu.io.in.fire))
54  }
55  val aluFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(AluCfg)).map(_.io.in.fire)
56  for (i <- 0 until (aluFireSeq.size + 1)){
57    XSPerfAccumulate(s"alu_fire_${i}_cnt", PopCount(aluFireSeq) === i.U)
58  }
59  val brhFireSeq = exus.filter(_.wrapper.exuParams.fuConfigs.contains(BrhCfg)).map(_.io.in.fire)
60  for (i <- 0 until (brhFireSeq.size + 1)) {
61    XSPerfAccumulate(s"brh_fire_${i}_cnt", PopCount(brhFireSeq) === i.U)
62  }
63}
64
65class ExuBlockIO(implicit p: Parameters, params: SchdBlockParams) extends XSBundle {
66  val flush = Flipped(ValidIO(new Redirect))
67  // in(i)(j): issueblock(i), exu(j)
68  val in: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(params.genExuInputBundle)
69  // out(i)(j): issueblock(i), exu(j).
70  val out: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = params.genExuOutputDecoupledBundle
71
72  val csrio = Option.when(params.hasCSR)(new CSRFileIO)
73  val csrin = Option.when(params.hasCSR)(new CSRInput)
74
75  val fenceio = Option.when(params.hasFence)(new FenceIO)
76  val frm = Option.when(params.needSrcFrm)(Input(Frm()))
77  val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm()))
78  val vtype = Option.when(params.writeVConfig)((Valid(new VType)))
79  val vlIsZero = Option.when(params.writeVConfig)(Output(Bool()))
80  val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool()))
81}
82