1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20)( 21 implicit 22 val schdType: SchedulerType, 23) { 24 // calculated configs 25 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 26 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 27 // used in bypass to select data of exu output 28 var exuIdx: Int = -1 29 var backendParam: BackendParams = null 30 31 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 32 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 33 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 34 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 35 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 36 val numSrc: Int = fuConfigs.map(_.numSrc).max 37 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 38 val readIntRf: Boolean = numIntSrc > 0 39 val readFpRf: Boolean = numFpSrc > 0 40 val readVecRf: Boolean = numVecSrc > 0 41 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 42 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 43 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 44 val writeVfRf: Boolean = writeFpRf || writeVecRf 45 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 46 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 47 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 48 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 49 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 50 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 51 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 52 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 53 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 54 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 55 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 56 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 57 val needTarget: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 58 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 59 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 60 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 61 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 62 63 def rdPregIdxWidth: Int = { 64 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 65 } 66 67 def wbPregIdxWidth: Int = { 68 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 69 } 70 71 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 72 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 73 74 /** 75 * Check if this exu has certain latency 76 */ 77 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 78 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 79 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 80 // only load use it 81 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 82 83 /** 84 * Get mapping from FuType to Latency value. 85 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 86 * 87 * @return Map[ [[BigInt]], Latency] 88 */ 89 def fuLatencyMap: Map[FuType.OHType, Int] = { 90 if (latencyCertain) 91 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 92 else if (hasUncertainLatencyVal) 93 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 94 else 95 Map() 96 } 97 98 /** 99 * Get set of latency of function units. 100 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 101 * 102 * @return Set[Latency] 103 */ 104 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 105 106 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 107 108 def intFuLatencyMap: Map[FuType.OHType, Int] = { 109 if (intLatencyCertain) 110 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 111 else 112 Map() 113 } 114 115 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 116 117 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 118 if (vfLatencyCertain) 119 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 120 else 121 Map() 122 } 123 124 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 125 126 /** 127 * Check if this exu has fixed latency 128 */ 129 def isFixedLatency: Boolean = { 130 if (latencyCertain) 131 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 132 false 133 } 134 135 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 136 137 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 138 139 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 140 141 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 142 143 def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _) 144 145 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 146 147 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 148 149 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 150 151 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu 152 153 def hasHybridAddrFu = hasLoadFu && hasStoreAddrFu 154 155 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 156 157 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 158 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 159 } 160 161 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 162 163 def getWBSource: SchedulerType = { 164 schdType 165 } 166 167 def hasCrossWb: Boolean = { 168 schdType match { 169 case IntScheduler() => writeFpRf || writeVecRf 170 case VfScheduler() => writeIntRf 171 case _ => false 172 } 173 } 174 175 def canAccept(fuType: UInt): Bool = { 176 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 177 } 178 179 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 180 181 def bindBackendParam(param: BackendParams): Unit = { 182 backendParam = param 183 } 184 185 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 186 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 187 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 188 if (this.isIQWakeUpSource) { 189 require(!this.hasUncertainLatency || hasLoadFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 190 } 191 } 192 193 def updateExuIdx(idx: Int): Unit = { 194 this.exuIdx = idx 195 } 196 197 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 198 199 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 200 201 def getIntWBPort = { 202 wbPortConfigs.collectFirst { 203 case x: IntWB => x 204 } 205 } 206 207 def getVfWBPort = { 208 wbPortConfigs.collectFirst { 209 case x: VfWB => x 210 } 211 } 212 213 /** 214 * Get the [[DataConfig]] that this exu need to read 215 */ 216 def pregRdDataCfgSet: Set[DataConfig] = { 217 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 218 } 219 220 /** 221 * Get the [[DataConfig]] that this exu need to write 222 */ 223 def pregWbDataCfgSet: Set[DataConfig] = { 224 this.wbPortConfigs.map(_.dataCfg).toSet 225 } 226 227 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 228 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 229 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 230 231 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 232 233 exuSrcsCfgSet 234 } 235 236 /** 237 * Get the [[DataConfig]] mapped indices of source data of exu 238 * 239 * @example 240 * {{{ 241 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 242 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 243 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 244 * getRfReadSrcIdx(VConfigData()) = Seq(4) 245 * }}} 246 * @return Map[DataConfig -> Seq[indices]] 247 */ 248 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 249 val dataCfgs = DataConfig.RegSrcDataSet 250 val rfRdDataCfgSet = this.getRfReadDataCfgSet 251 dataCfgs.toSeq.map { cfg => 252 ( 253 cfg, 254 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 255 if (set.contains(cfg)) 256 Option(srcIdx) 257 else 258 None 259 }.filter(_.nonEmpty).map(_.get) 260 ) 261 }.toMap 262 } 263 264 def genExuModule(implicit p: Parameters): ExeUnit = { 265 new ExeUnit(this) 266 } 267 268 def genExuInputBundle(implicit p: Parameters): ExuInput = { 269 new ExuInput(this) 270 } 271 272 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 273 new ExuOutput(this) 274 } 275 276 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 277 new ExuBypassBundle(this) 278 } 279} 280