1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20 fakeUnit : Boolean = false, 21)( 22 implicit 23 val schdType: SchedulerType, 24) { 25 // calculated configs 26 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 27 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 28 // used in bypass to select data of exu output 29 var exuIdx: Int = -1 30 var backendParam: BackendParams = null 31 32 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 33 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 34 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 35 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 36 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 37 val numSrc: Int = fuConfigs.map(_.numSrc).max 38 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 39 val readIntRf: Boolean = numIntSrc > 0 40 val readFpRf: Boolean = numFpSrc > 0 41 val readVecRf: Boolean = numVecSrc > 0 42 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 43 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 44 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 45 val writeVfRf: Boolean = writeFpRf || writeVecRf 46 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 47 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 48 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 49 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 50 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 51 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 52 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 53 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 54 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 55 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 56 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 57 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 58 val needTarget: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 60 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 61 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 62 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 63 64 def rdPregIdxWidth: Int = { 65 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 66 } 67 68 def wbPregIdxWidth: Int = { 69 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 70 } 71 72 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 73 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 74 75 /** 76 * Check if this exu has certain latency 77 */ 78 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 79 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 80 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 81 // only load use it 82 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 83 84 /** 85 * Get mapping from FuType to Latency value. 86 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 87 * 88 * @return Map[ [[BigInt]], Latency] 89 */ 90 def fuLatencyMap: Map[FuType.OHType, Int] = { 91 if (latencyCertain) 92 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 93 else if (hasUncertainLatencyVal) 94 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 95 else 96 Map() 97 } 98 99 /** 100 * Get set of latency of function units. 101 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 102 * 103 * @return Set[Latency] 104 */ 105 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 106 107 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 108 109 def intFuLatencyMap: Map[FuType.OHType, Int] = { 110 if (intLatencyCertain) 111 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 112 else 113 Map() 114 } 115 116 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 117 118 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 119 if (vfLatencyCertain) 120 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 121 else 122 Map() 123 } 124 125 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 126 127 /** 128 * Check if this exu has fixed latency 129 */ 130 def isFixedLatency: Boolean = { 131 if (latencyCertain) 132 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 133 false 134 } 135 136 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 137 138 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 139 140 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 141 142 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 143 144 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 145 146 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 147 148 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 149 150 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 151 152 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu 153 154 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 155 156 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 157 158 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 159 160 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 161 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 162 } 163 164 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 165 166 def getWBSource: SchedulerType = { 167 schdType 168 } 169 170 def hasCrossWb: Boolean = { 171 schdType match { 172 case IntScheduler() => writeFpRf || writeVecRf 173 case VfScheduler() => writeIntRf 174 case _ => false 175 } 176 } 177 178 def canAccept(fuType: UInt): Bool = { 179 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 180 } 181 182 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 183 184 def bindBackendParam(param: BackendParams): Unit = { 185 backendParam = param 186 } 187 188 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 189 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 190 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 191 if (this.isIQWakeUpSource) { 192 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 193 } 194 } 195 196 def updateExuIdx(idx: Int): Unit = { 197 this.exuIdx = idx 198 } 199 200 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 201 202 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 203 204 def getIntWBPort = { 205 wbPortConfigs.collectFirst { 206 case x: IntWB => x 207 } 208 } 209 210 def getVfWBPort = { 211 wbPortConfigs.collectFirst { 212 case x: VfWB => x 213 } 214 } 215 216 /** 217 * Get the [[DataConfig]] that this exu need to read 218 */ 219 def pregRdDataCfgSet: Set[DataConfig] = { 220 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 221 } 222 223 /** 224 * Get the [[DataConfig]] that this exu need to write 225 */ 226 def pregWbDataCfgSet: Set[DataConfig] = { 227 this.wbPortConfigs.map(_.dataCfg).toSet 228 } 229 230 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 231 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 232 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 233 234 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 235 236 exuSrcsCfgSet 237 } 238 239 /** 240 * Get the [[DataConfig]] mapped indices of source data of exu 241 * 242 * @example 243 * {{{ 244 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 245 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 246 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 247 * getRfReadSrcIdx(VConfigData()) = Seq(4) 248 * }}} 249 * @return Map[DataConfig -> Seq[indices]] 250 */ 251 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 252 val dataCfgs = DataConfig.RegSrcDataSet 253 val rfRdDataCfgSet = this.getRfReadDataCfgSet 254 dataCfgs.toSeq.map { cfg => 255 ( 256 cfg, 257 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 258 if (set.contains(cfg)) 259 Option(srcIdx) 260 else 261 None 262 }.filter(_.nonEmpty).map(_.get) 263 ) 264 }.toMap 265 } 266 267 def genExuModule(implicit p: Parameters): ExeUnit = { 268 new ExeUnit(this) 269 } 270 271 def genExuInputBundle(implicit p: Parameters): ExuInput = { 272 new ExuInput(this) 273 } 274 275 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 276 new ExuOutput(this) 277 } 278 279 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 280 new ExuBypassBundle(this) 281 } 282} 283