1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.DelayN 8import utils._ 9import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 10import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 11import xiangshan.{Redirect, XSBundle, XSModule} 12 13class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 14 val flush = Flipped(ValidIO(new Redirect())) 15 val in = Flipped(DecoupledIO(new ExuInput(params))) 16 val out = DecoupledIO(new ExuOutput(params)) 17 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 18 val fenceio = if (params.hasFence) Some(new FenceIO) else None 19 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 20} 21 22class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 23 lazy val module = new ExeUnitImp(this)(p, exuParams) 24} 25 26class ExeUnitImp( 27 override val wrapper: ExeUnit 28)(implicit 29 p: Parameters, exuParams: ExeUnitParams 30) extends LazyModuleImp(wrapper) { 31 private val fuCfgs = exuParams.fuConfigs 32 33 val io = IO(new ExeUnitIO(exuParams)) 34 35 val funcUnits = fuCfgs.map(cfg => { 36 val module = cfg.fuGen(p, cfg) 37 module 38 }) 39 40 val busy = RegInit(false.B) 41 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 42 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 43 busy := false.B 44 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 45 busy := false.B 46 }.elsewhen(io.out.fire) { 47 busy := false.B 48 }.elsewhen(io.in.fire) { 49 busy := true.B 50 } 51 if(exuParams.latencyValMax.nonEmpty){ 52 busy := false.B 53 } 54 55 // rob flush --> funcUnits 56 funcUnits.zipWithIndex.foreach { case (fu, i) => 57 fu.io.flush <> io.flush 58 } 59 60 def acceptCond(input: ExuInput): Seq[Bool] = { 61 input.params.fuConfigs.map(_.fuSel(input)) 62 } 63 64 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 65 66 // ExeUnit.in <---> Dispatcher.in 67 in1ToN.io.in.valid := io.in.fire() 68 in1ToN.io.in.bits := io.in.bits 69 io.in.ready := !busy 70 71 // Dispatcher.out <---> FunctionUnits 72 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 73 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 74 sink.valid := source.valid 75 source.ready := sink.ready 76 77 sink.bits.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 78 sink.bits.fuOpType := source.bits.fuOpType 79 sink.bits.imm := source.bits.imm 80 sink.bits.robIdx := source.bits.robIdx 81 sink.bits.pdest := source.bits.pdest 82 sink.bits.rfWen .foreach(x => x := source.bits.rfWen.get) 83 sink.bits.fpWen .foreach(x => x := source.bits.fpWen.get) 84 sink.bits.vecWen .foreach(x => x := source.bits.vecWen.get) 85 sink.bits.fpu .foreach(x => x := source.bits.fpu.get) 86 sink.bits.flushPipe .foreach(x => x := source.bits.flushPipe.get) 87 sink.bits.pc .foreach(x => x := source.bits.pc.get) 88 sink.bits.preDecode .foreach(x => x := source.bits.preDecode.get) 89 sink.bits.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 90 sink.bits.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 91 sink.bits.predictInfo .foreach(x => x := source.bits.predictInfo.get) 92 } 93 94 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 95 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 96 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 97 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.redirect) 98 99 // Assume that one fu can only write int or fp or vec, 100 // otherwise, wenVec should be assigned to wen in fu. 101 private val fuIntWenVec = funcUnits.map(_.cfg.writeIntRf.B) 102 private val fuFpWenVec = funcUnits.map(_.cfg.writeFpRf.B) 103 private val fuVecWenVec = funcUnits.map(_.cfg.writeVecRf.B) 104 // FunctionUnits <---> ExeUnit.out 105 io.out.valid := Cat(fuOutValidOH).orR 106 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 107 108 // select one fu's result 109 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.data)) 110 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.robIdx)) 111 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.pdest)) 112 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 113 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 114 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 115 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 116 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 117 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 118 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 119 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 120 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 121 122 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 123 fuio => 124 exuio <> fuio 125 fuio.exception := DelayN(exuio.exception, 2) 126 })) 127 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 128 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 129 130 // debug info 131 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 132 io.out.bits.debugInfo := 0.U.asTypeOf(io.out.bits.debugInfo) 133} 134 135class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 136 val in = Flipped(DecoupledIO(gen)) 137 138 val out = Vec(n, DecoupledIO(gen)) 139} 140 141class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 142 (implicit p: Parameters) 143 extends Module { 144 145 val io = IO(new DispatcherIO(gen, n)) 146 147 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 148 149 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 150 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 151 152 io.out.zipWithIndex.foreach { case (out, i) => 153 out.valid := acceptVec(i) && io.in.valid && out.ready 154 out.bits := io.in.bits 155 } 156 157 io.in.ready := Cat(io.out.map(_.ready)).orR 158} 159 160class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 161 val flush = Flipped(ValidIO(new Redirect())) 162 val in = Flipped(DecoupledIO(new MemExuInput())) 163 val out = DecoupledIO(new MemExuOutput()) 164} 165 166class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 167 val io = IO(new MemExeUnitIO) 168 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 169 fu.io.flush := io.flush 170 fu.io.in.valid := io.in.valid 171 io.in.ready := fu.io.in.ready 172 173 fu.io.in.bits.robIdx := io.in.bits.uop.robIdx 174 fu.io.in.bits.pdest := io.in.bits.uop.pdest 175 fu.io.in.bits.fuOpType := io.in.bits.uop.fuOpType 176 fu.io.in.bits.imm := io.in.bits.uop.imm 177 fu.io.in.bits.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 178 179 io.out.valid := fu.io.out.valid 180 fu.io.out.ready := io.out.ready 181 182 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 183 io.out.bits.data := fu.io.out.bits.data 184 io.out.bits.uop.robIdx := fu.io.out.bits.robIdx 185 io.out.bits.uop.pdest := fu.io.out.bits.pdest 186 io.out.bits.uop.fuType := io.in.bits.uop.fuType 187 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 188 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 189 190 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 191} 192