1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.experimental.hierarchy.{Definition, instantiable, public} 23import chisel3.util._ 24import utils._ 25import utility._ 26import xiangshan._ 27import xiangshan.backend.fu.fpu.{FMA, FPUSubModule} 28import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer} 29import xiangshan.backend.fu.vector.VFPU 30 31class FenceIO(implicit p: Parameters) extends XSBundle { 32 val sfence = Output(new SfenceBundle) 33 val fencei = Output(Bool()) 34 val sbuffer = new FenceToSbuffer 35} 36 37@instantiable 38class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { 39 40 val disableSfence = WireInit(false.B) 41 val csr_frm = WireInit(frm.getOrElse(0.U(3.W))) 42 43 val hasRedirect = config.fuConfigs.zip(functionUnits).filter(_._1.hasRedirect).map(_._2) 44 println(s"ExeUnit: ${functionUnits.map(_.name).reduce(_ + " " + _)} ${hasRedirect} hasRedirect: ${hasRedirect.length}") 45 if (hasRedirect.nonEmpty) { 46 require(hasRedirect.length <= 1) 47 io.out.bits.redirectValid := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOutValid 48 io.out.bits.redirect := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOut 49 } 50 51 if (config.fuConfigs.contains(csrCfg)) { 52 val csr = functionUnits.collectFirst{ 53 case c: CSR => c 54 }.get 55 csr.csrio <> csrio.get 56 csrio.get.tlb := DelayN(csr.csrio.tlb, 2) 57 csrio.get.customCtrl := DelayN(csr.csrio.customCtrl, 2) 58 csrio.get.trapTarget := RegNext(csr.csrio.trapTarget) 59 csr.csrio.exception := DelayN(csrio.get.exception, 2) 60 disableSfence := csr.csrio.disableSfence 61 csr_frm := csr.csrio.fpu.frm 62 // setup skip for hpm CSR read 63 io.out.bits.debug.isPerfCnt := RegNext(csr.csrio.isPerfCnt) // TODO: this is dirty 64 } 65 66 if (config.fuConfigs.contains(fenceCfg)) { 67 val fence = functionUnits.collectFirst{ 68 case f: Fence => f 69 }.get 70 fenceio.get.sfence <> fence.sfence 71 fenceio.get.fencei <> fence.fencei 72 fenceio.get.sbuffer <> fence.toSbuffer 73 fence.io.out.ready := true.B 74 fence.disableSfence := disableSfence 75 } 76 77 val fpModules = functionUnits.zip(config.fuConfigs.zipWithIndex).filter(_._1.isInstanceOf[FPUSubModule]) 78 val vfpModules = functionUnits.zip(config.fuConfigs.zipWithIndex).filter(_._1.isInstanceOf[VFPU]) 79 if (fpModules.nonEmpty) { 80 // frm is from csr/frm (from CSR) or instr_rm (from instruction decoding) 81 val fpSubModules = fpModules.map(_._1.asInstanceOf[FPUSubModule]) 82 fpSubModules.foreach(mod => { 83 val instr_rm = mod.io.in.bits.uop.ctrl.fpu.rm 84 mod.rm := Mux(instr_rm =/= 7.U, instr_rm, csr_frm) 85 }) 86 // fflags is selected by arbSelReg 87 require(config.hasFastUopOut, "non-fast not implemented") 88 val fflagsSel = fpModules.map{ case (fu, (cfg, i)) => 89 val fflagsValid = arbSelReg(i) 90 val fflags = fu.asInstanceOf[FPUSubModule].fflags 91 val fflagsBits = if (cfg.fastImplemented) fflags else RegNext(fflags) 92 (fflagsValid, fflagsBits) 93 } 94 io.out.bits.fflags := Mux1H(fflagsSel.map(_._1), fflagsSel.map(_._2)) 95 } 96 // Overwrite write operation of fpModules 97 if (vfpModules.nonEmpty) { 98 val vfpSubModules = vfpModules.map(_._1.asInstanceOf[VFPU]) 99 vfpSubModules.foreach(mod => { 100 val instr_rm = mod.io.in.bits.uop.ctrl.fpu.rm 101 mod.rm := csr_frm 102 }) 103 } 104 val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA]) 105 if (fmaModules.nonEmpty) { 106 require(fmaModules.length == 1) 107 } 108 109 if (config.readIntRf) { 110 val in = io.fromInt 111 val out = io.out 112 XSDebug(in.valid, p"fromInt(${in.valid} ${in.ready}) toInt(${out.valid} ${out.ready})\n") 113 XSDebug(io.redirect.valid, p"Redirect:(${io.redirect.valid}) robIdx:${io.redirect.bits.robIdx}\n") 114 XSDebug(in.valid, p"src1:${Hexadecimal(in.bits.src(0))} src2:${Hexadecimal(in.bits.src(1))} " + 115 p"func:${Binary(in.bits.uop.ctrl.fuOpType)} pc:${Hexadecimal(in.bits.uop.cf.pc)} robIdx:${in.bits.uop.robIdx}\n") 116 XSDebug(out.valid, p"out res:${Hexadecimal(out.bits.data)} robIdx:${out.bits.uop.robIdx}\n") 117 } 118 119} 120 121class AluExeUnit(implicit p: Parameters) extends ExeUnit(AluExeUnitCfg) 122class JumpCSRExeUnit(implicit p: Parameters) extends ExeUnit(JumpCSRExeUnitCfg) 123class JumpExeUnit(implicit p: Parameters) extends ExeUnit(JumpExeUnitCfg) 124class StdExeUnit(implicit p: Parameters) extends ExeUnit(StdExeUnitCfg) 125class FmacExeUnit(implicit p: Parameters) extends ExeUnit(FmacExeUnitCfg) 126class FmiscExeUnit(implicit p: Parameters) extends ExeUnit(FmiscExeUnitCfg) 127 128object ExeUnitDef { 129 def apply(cfg: ExuConfig)(implicit p: Parameters): Definition[ExeUnit] = { 130 cfg match { 131 case JumpExeUnitCfg => Definition(new JumpExeUnit) 132 case AluExeUnitCfg => Definition(new AluExeUnit) 133 case MulDivExeUnitCfg => Definition(new MulDivExeUnit) 134 case JumpCSRExeUnitCfg => Definition(new JumpCSRExeUnit) 135 case FmacExeUnitCfg => Definition(new FmacExeUnit) 136 case FmiscExeUnitCfg => Definition(new FmiscExeUnit) 137 case _ => { 138 println(s"cannot generate exeUnit from $cfg") 139 null 140 } 141 } 142 } 143} 144 145