1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.DelayN 8import utils._ 9import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 10import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 11import xiangshan.{Redirect, XSBundle, XSModule} 12 13class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 14 val flush = Flipped(ValidIO(new Redirect())) 15 val in = Flipped(DecoupledIO(new ExuInput(params))) 16 val out = DecoupledIO(new ExuOutput(params)) 17 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 18 val fenceio = if (params.hasFence) Some(new FenceIO) else None 19 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 20} 21 22class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 23 lazy val module = new ExeUnitImp(this)(p, exuParams) 24} 25 26class ExeUnitImp( 27 override val wrapper: ExeUnit 28)(implicit 29 p: Parameters, exuParams: ExeUnitParams 30) extends LazyModuleImp(wrapper) { 31 private val fuCfgs = exuParams.fuConfigs 32 33 val io = IO(new ExeUnitIO(exuParams)) 34 35 val funcUnits = fuCfgs.map(cfg => { 36 val module = cfg.fuGen(p, cfg) 37 module 38 }) 39 40 val busy = RegInit(false.B) 41 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 42 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 43 busy := false.B 44 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 45 busy := false.B 46 }.elsewhen(io.out.fire) { 47 busy := false.B 48 }.elsewhen(io.in.fire) { 49 busy := true.B 50 } 51 52 // rob flush --> funcUnits 53 funcUnits.zipWithIndex.foreach { case (fu, i) => 54 fu.io.flush <> io.flush 55 } 56 57 def acceptCond(input: ExuInput): Seq[Bool] = { 58 input.params.fuConfigs.map(_.fuSel(input)) 59 } 60 61 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 62 63 // ExeUnit.in <---> Dispatcher.in 64 in1ToN.io.in.valid := io.in.valid && !busy 65 in1ToN.io.in.bits := io.in.bits 66 io.in.ready := !busy 67 68 // Dispatcher.out <---> FunctionUnits 69 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 70 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 71 sink.valid := source.valid 72 source.ready := sink.ready 73 74 sink.bits.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 75 sink.bits.fuOpType := source.bits.fuOpType 76 sink.bits.imm := source.bits.imm 77 sink.bits.robIdx := source.bits.robIdx 78 sink.bits.pdest := source.bits.pdest 79 sink.bits.rfWen .foreach(x => x := source.bits.rfWen.get) 80 sink.bits.fpWen .foreach(x => x := source.bits.fpWen.get) 81 sink.bits.vecWen .foreach(x => x := source.bits.vecWen.get) 82 sink.bits.fpu .foreach(x => x := source.bits.fpu.get) 83 sink.bits.flushPipe .foreach(x => x := source.bits.flushPipe.get) 84 sink.bits.pc .foreach(x => x := source.bits.pc.get) 85 sink.bits.preDecode .foreach(x => x := source.bits.preDecode.get) 86 sink.bits.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 87 sink.bits.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 88 sink.bits.predictInfo .foreach(x => x := source.bits.predictInfo.get) 89 } 90 91 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 92 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 93 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.redirect) 94 95 // Assume that one fu can only write int or fp or vec, 96 // otherwise, wenVec should be assigned to wen in fu. 97 private val fuIntWenVec = funcUnits.map(_.cfg.writeIntRf.B) 98 private val fuFpWenVec = funcUnits.map(_.cfg.writeFpRf.B) 99 private val fuVecWenVec = funcUnits.map(_.cfg.writeVecRf.B) 100 // FunctionUnits <---> ExeUnit.out 101 io.out.valid := Cat(fuOutValidOH).orR 102 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 103 104 // select one fu's result 105 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.data)) 106 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.robIdx)) 107 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.pdest)) 108 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 109 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 110 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 111 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 112 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 113 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 114 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 115 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 116 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 117 118 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 119 fuio => 120 exuio <> fuio 121 fuio.exception := DelayN(exuio.exception, 2) 122 })) 123 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 124 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 125 126 // debug info 127 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 128 io.out.bits.debugInfo := 0.U.asTypeOf(io.out.bits.debugInfo) 129} 130 131class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 132 val in = Flipped(DecoupledIO(gen)) 133 134 val out = Vec(n, DecoupledIO(gen)) 135} 136 137class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 138 (implicit p: Parameters) 139 extends Module { 140 141 val io = IO(new DispatcherIO(gen, n)) 142 143 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 144 145 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 146 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 147 148 io.out.zipWithIndex.foreach { case (out, i) => 149 out.valid := acceptVec(i) && io.in.valid && out.ready 150 out.bits := io.in.bits 151 } 152 153 io.in.ready := Cat(io.out.map(_.ready)).orR 154} 155 156class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 157 val flush = Flipped(ValidIO(new Redirect())) 158 val in = Flipped(DecoupledIO(new MemExuInput())) 159 val out = DecoupledIO(new MemExuOutput()) 160} 161 162class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 163 val io = IO(new MemExeUnitIO) 164 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 165 fu.io.flush := io.flush 166 fu.io.in.valid := io.in.valid 167 io.in.ready := fu.io.in.ready 168 169 fu.io.in.bits.robIdx := io.in.bits.uop.robIdx 170 fu.io.in.bits.pdest := io.in.bits.uop.pdest 171 fu.io.in.bits.fuOpType := io.in.bits.uop.fuOpType 172 fu.io.in.bits.imm := io.in.bits.uop.imm 173 fu.io.in.bits.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 174 175 io.out.valid := fu.io.out.valid 176 fu.io.out.ready := io.out.ready 177 178 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 179 io.out.bits.data := fu.io.out.bits.data 180 io.out.bits.uop.robIdx := fu.io.out.bits.robIdx 181 io.out.bits.uop.pdest := fu.io.out.bits.pdest 182 io.out.bits.uop.fuType := io.in.bits.uop.fuType 183 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 184 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 185 186 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 187} 188