1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.dispatch 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.MemCoreTopDownIO 26import xiangshan.backend.rob.{RobDispatchTopDownIO, RobEnqIO} 27import xiangshan.mem.mdp._ 28import xiangshan.mem.{HasVLSUParameters, _} 29import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExuOH, ExuVec, IssueQueueIQWakeUpBundle} 30import xiangshan.backend.fu.{FuConfig, FuType} 31import xiangshan.backend.rename.BusyTable 32import chisel3.util.experimental.decode._ 33import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 34import xiangshan.backend.fu.{FuConfig, FuType} 35import xiangshan.backend.rename.BusyTableReadIO 36import xiangshan.backend.datapath.DataConfig._ 37import xiangshan.backend.datapath.WbConfig._ 38import xiangshan.backend.datapath.DataSource 39import xiangshan.backend.datapath.WbConfig.VfWB 40import xiangshan.backend.fu.FuType.FuTypeOrR 41import xiangshan.backend.dispatch.Dispatch2IqFpImp 42import xiangshan.backend.regcache.{RCTagTableReadPort, RegCacheTagTable} 43 44 45// TODO delete trigger message from frontend to iq 46class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents with HasVLSUParameters { 47 // std IQ donot need dispatch, only copy sta IQ, but need sta IQ's ready && std IQ's ready 48 val allIssueParams = backendParams.allIssueParams.filter(_.StdCnt == 0) 49 val allExuParams = allIssueParams.map(_.exuBlockParams).flatten 50 val allFuConfigs = allExuParams.map(_.fuConfigs).flatten.toSet.toSeq 51 val sortedFuConfigs = allFuConfigs.sortBy(_.fuType.id) 52 println(s"[NewDispatch] ${allExuParams.map(_.name)}") 53 println(s"[NewDispatch] ${allFuConfigs.map(_.name)}") 54 println(s"[NewDispatch] ${allFuConfigs.map(_.fuType.id)}") 55 println(s"[NewDispatch] ${sortedFuConfigs.map(_.name)}") 56 println(s"[NewDispatch] ${sortedFuConfigs.map(_.fuType.id)}") 57 val fuConfigsInIssueParams = allIssueParams.map(_.allExuParams.map(_.fuConfigs).flatten.toSet.toSeq) 58 val fuMapIQIdx = sortedFuConfigs.map( fu => { 59 val fuInIQIdx = fuConfigsInIssueParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 60 (fu -> fuInIQIdx) 61 } 62 ) 63 fuMapIQIdx.map { case (fu, iqidx) => 64 println(s"[NewDispatch] ${fu.name} $iqidx") 65 } 66 val sameIQIdxFus = fuMapIQIdx.map{ case (fu, iqidx) => 67 fuMapIQIdx.filter(_._2 == iqidx).map(_._1) -> iqidx 68 }.toSet.toSeq 69 val needMultiIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1) 70 val needSingleIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size == 1) 71 needMultiIQ.map { case (fus, iqidx) => 72 println(s"[NewDispatch] needMultiIQ: ${fus.map(_.name)} $iqidx") 73 } 74 needSingleIQ.map { case (fus, iqidx) => 75 println(s"[NewDispatch] needSingleIQ: ${fus.map(_.name)} $iqidx") 76 } 77 val fuConfigsInExuParams = allExuParams.map(_.fuConfigs) 78 val fuMapExuIdx = sortedFuConfigs.map { case fu => { 79 val fuInExuIdx = fuConfigsInExuParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 80 (fu -> fuInExuIdx) 81 } 82 } 83 val sameExuIdxFus = fuMapExuIdx.map { case (fu, exuidx) => 84 fuMapExuIdx.filter(_._2 == exuidx).map(_._1) -> exuidx 85 }.toSet.toSeq 86 val needMultiExu = sameExuIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1).filter{ x => 87 x._1.map(y => fuMapIQIdx.filter(_._1 == y).head._2.size > 1).reduce(_ && _) 88 } 89 90 val exuNum = allExuParams.size 91 val maxIQSize = allIssueParams.map(_.numEntries).max 92 val IQEnqSum = allIssueParams.map(_.numEnq).sum 93 94 val io = IO(new Bundle { 95 // from rename 96 val renameIn = Vec(RenameWidth, Flipped(ValidIO(new DecodedInst))) 97 val fromRename = Vec(RenameWidth, Flipped(DecoupledIO(new DynInst))) 98 val toRenameAllFire = Output(Bool()) 99 // enq Rob 100 val enqRob = Flipped(new RobEnqIO) 101 // IssueQueues 102 val IQValidNumVec = Vec(exuNum, Input(UInt(maxIQSize.U.getWidth.W))) 103 val toIssueQueues = Vec(IQEnqSum, DecoupledIO(new DynInst)) 104 // to busyTable 105 // set preg state to ready (write back regfile) 106 val wbPregsInt = Vec(backendParams.numPregWb(IntData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 107 val wbPregsFp = Vec(backendParams.numPregWb(FpData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 108 val wbPregsVec = Vec(backendParams.numPregWb(VecData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 109 val wbPregsV0 = Vec(backendParams.numPregWb(V0Data()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 110 val wbPregsVl = Vec(backendParams.numPregWb(VlData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 111 val wakeUpAll = new Bundle { 112 val wakeUpInt: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.intSchdParams.get.genIQWakeUpOutValidBundle) 113 val wakeUpFp: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.fpSchdParams.get.genIQWakeUpOutValidBundle) 114 val wakeUpVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.vfSchdParams.get.genIQWakeUpOutValidBundle) 115 val wakeUpMem: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.memSchdParams.get.genIQWakeUpOutValidBundle) 116 } 117 val og0Cancel = Input(ExuVec()) 118 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 119 // from MemBlock 120 val fromMem = new Bundle { 121 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 122 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 123 val lqDeqPtr = Input(new LqPtr) 124 val sqDeqPtr = Input(new SqPtr) 125 // from lsq 126 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 127 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 128 } 129 //toMem 130 val toMem = new Bundle { 131 val lsqEnqIO = Flipped(new LsqEnqIO) 132 } 133 // redirect 134 val redirect = Flipped(ValidIO(new Redirect)) 135 // singleStep 136 val singleStep = Input(Bool()) 137 // lfst 138 val lfst = new DispatchLFSTIO 139 140 // perf only 141 val robHead = Input(new DynInst) 142 val stallReason = Flipped(new StallReasonIO(RenameWidth)) 143 val lqCanAccept = Input(Bool()) 144 val sqCanAccept = Input(Bool()) 145 val robHeadNotReady = Input(Bool()) 146 val robFull = Input(Bool()) 147 val debugTopDown = new Bundle { 148 val fromRob = Flipped(new RobDispatchTopDownIO) 149 val fromCore = new CoreDispatchTopDownIO 150 } 151 }) 152 // Deq for std's IQ is not assigned in Dispatch2Iq, so add one more src for it. 153 val issueBlockParams = backendParams.allIssueParams 154 val renameIn = io.renameIn 155 val fromRename = io.fromRename 156 io.toRenameAllFire := io.fromRename.map(x => !x.valid || x.fire).reduce(_ && _) 157 val fromRenameUpdate = Wire(Vec(RenameWidth, Flipped(ValidIO(new DynInst)))) 158 fromRenameUpdate := fromRename 159 val renameWidth = io.fromRename.size 160 val issueQueueCount = io.IQValidNumVec 161 val issueQueueNum = allIssueParams.size 162 // int fp vec v0 vl 163 val numRegType = 5 164 val idxRegTypeInt = allFuConfigs.map(x => { 165 x.srcData.map(xx => { 166 xx.zipWithIndex.filter(y => IntRegSrcDataSet.contains(y._1)).map(_._2) 167 }).flatten 168 }).flatten.toSet.toSeq.sorted 169 val idxRegTypeFp = allFuConfigs.map(x => { 170 x.srcData.map(xx => { 171 xx.zipWithIndex.filter(y => FpRegSrcDataSet.contains(y._1)).map(_._2) 172 }).flatten 173 }).flatten.toSet.toSeq.sorted 174 val idxRegTypeVec = allFuConfigs.map(x => { 175 x.srcData.map(xx => { 176 xx.zipWithIndex.filter(y => VecRegSrcDataSet.contains(y._1)).map(_._2) 177 }).flatten 178 }).flatten.toSet.toSeq.sorted 179 val idxRegTypeV0 = allFuConfigs.map(x => { 180 x.srcData.map(xx => { 181 xx.zipWithIndex.filter(y => V0RegSrcDataSet.contains(y._1)).map(_._2) 182 }).flatten 183 }).flatten.toSet.toSeq.sorted 184 val idxRegTypeVl = allFuConfigs.map(x => { 185 x.srcData.map(xx => { 186 xx.zipWithIndex.filter(y => VlRegSrcDataSet.contains(y._1)).map(_._2) 187 }).flatten 188 }).flatten.toSet.toSeq.sorted 189 println(s"[NewDispatch] idxRegTypeInt: $idxRegTypeInt") 190 println(s"[NewDispatch] idxRegTypeFp: $idxRegTypeFp") 191 println(s"[NewDispatch] idxRegTypeVec: $idxRegTypeVec") 192 println(s"[NewDispatch] idxRegTypeV0: $idxRegTypeV0") 193 println(s"[NewDispatch] idxRegTypeVl: $idxRegTypeVl") 194 val numRegSrc: Int = issueBlockParams.map(_.exuBlockParams.map( 195 x => if (x.hasStdFu) x.numRegSrc + 1 else x.numRegSrc 196 ).max).max 197 198 val numRegSrcInt: Int = issueBlockParams.map(_.exuBlockParams.map( 199 x => if (x.hasStdFu) x.numIntSrc + 1 else x.numIntSrc 200 ).max).max 201 val numRegSrcFp: Int = issueBlockParams.map(_.exuBlockParams.map( 202 x => if (x.hasStdFu) x.numFpSrc + 1 else x.numFpSrc 203 ).max).max 204 val numRegSrcVf: Int = issueBlockParams.map(_.exuBlockParams.map( 205 x => x.numVecSrc 206 ).max).max 207 val numRegSrcV0: Int = issueBlockParams.map(_.exuBlockParams.map( 208 x => x.numV0Src 209 ).max).max 210 val numRegSrcVl: Int = issueBlockParams.map(_.exuBlockParams.map( 211 x => x.numVlSrc 212 ).max).max 213 214 println(s"[Dispatch2Iq] numRegSrc: ${numRegSrc}, numRegSrcInt: ${numRegSrcInt}, numRegSrcFp: ${numRegSrcFp}, " + 215 s"numRegSrcVf: ${numRegSrcVf}, numRegSrcV0: ${numRegSrcV0}, numRegSrcVl: ${numRegSrcVl}") 216 217 // RegCacheTagTable Module 218 val rcTagTable = Module(new RegCacheTagTable(numRegSrcInt * renameWidth)) 219 // BusyTable Modules 220 val intBusyTable = Module(new BusyTable(numRegSrcInt * renameWidth, backendParams.numPregWb(IntData()), IntPhyRegs, IntWB())) 221 val fpBusyTable = Module(new BusyTable(numRegSrcFp * renameWidth, backendParams.numPregWb(FpData()), FpPhyRegs, FpWB())) 222 val vecBusyTable = Module(new BusyTable(numRegSrcVf * renameWidth, backendParams.numPregWb(VecData()), VfPhyRegs, VfWB())) 223 val v0BusyTable = Module(new BusyTable(numRegSrcV0 * renameWidth, backendParams.numPregWb(V0Data()), V0PhyRegs, V0WB())) 224 val vlBusyTable = Module(new BusyTable(numRegSrcVl * renameWidth, backendParams.numPregWb(VlData()), VlPhyRegs, VlWB())) 225 val busyTables = Seq(intBusyTable, fpBusyTable, vecBusyTable, v0BusyTable, vlBusyTable) 226 val wbPregs = Seq(io.wbPregsInt, io.wbPregsFp, io.wbPregsVec, io.wbPregsV0, io.wbPregsVl) 227 val idxRegType = Seq(idxRegTypeInt, idxRegTypeFp, idxRegTypeVec, idxRegTypeV0, idxRegTypeVl) 228 val allocPregsValid = Wire(Vec(busyTables.size, Vec(RenameWidth, Bool()))) 229 allocPregsValid(0) := VecInit(fromRename.map(x => x.valid && x.bits.rfWen && !x.bits.eliminatedMove)) 230 allocPregsValid(1) := VecInit(fromRename.map(x => x.valid && x.bits.fpWen)) 231 allocPregsValid(2) := VecInit(fromRename.map(x => x.valid && x.bits.vecWen)) 232 allocPregsValid(3) := VecInit(fromRename.map(x => x.valid && x.bits.v0Wen)) 233 allocPregsValid(4) := VecInit(fromRename.map(x => x.valid && x.bits.vlWen)) 234 val allocPregs = Wire(Vec(busyTables.size, Vec(RenameWidth, ValidIO(UInt(PhyRegIdxWidth.W))))) 235 allocPregs.zip(allocPregsValid).map(x =>{ 236 x._1.zip(x._2).zipWithIndex.map{case ((sink, source), i) => { 237 sink.valid := source 238 sink.bits := fromRename(i).bits.pdest 239 }} 240 }) 241 val wakeUp = io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpFp ++ io.wakeUpAll.wakeUpVec ++ io.wakeUpAll.wakeUpMem 242 busyTables.zip(wbPregs).zip(allocPregs).map{ case ((b, w), a) => { 243 b.io.wakeUpInt := io.wakeUpAll.wakeUpInt 244 b.io.wakeUpFp := io.wakeUpAll.wakeUpFp 245 b.io.wakeUpVec := io.wakeUpAll.wakeUpVec 246 b.io.wakeUpMem := io.wakeUpAll.wakeUpMem 247 b.io.og0Cancel := io.og0Cancel 248 b.io.ldCancel := io.ldCancel 249 b.io.wbPregs := w 250 b.io.allocPregs := a 251 }} 252 rcTagTable.io.allocPregs.zip(allocPregs(0)).map(x => x._1 := x._2) 253 rcTagTable.io.wakeupFromIQ := io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpMem 254 rcTagTable.io.og0Cancel := io.og0Cancel 255 rcTagTable.io.ldCancel := io.ldCancel 256 busyTables.zip(idxRegType).zipWithIndex.map { case ((b, idxseq), i) => { 257 val readAddr = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(_._1)).flatten) 258 val readValid = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(y => x.valid && SrcType.isXp(x.bits.srcType(y._2)))).flatten) 259 b.io.read.map(_.req).zip(readAddr).map(x => x._1 := x._2) 260 // only int src need srcLoadDependency, src0 src1 261 if (i == 0) { 262 val srcLoadDependencyUpdate = fromRenameUpdate.map(x => x.bits.srcLoadDependency.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 263 val srcType = fromRenameUpdate.map(x => x.bits.srcType.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 264 // for std, int src need srcLoadDependency, fp src donot need srcLoadDependency 265 srcLoadDependencyUpdate.lazyZip(b.io.read.map(_.loadDependency)).lazyZip(srcType).map{ case (sink, source, srctype) => 266 sink := Mux(SrcType.isXp(srctype), source, 0.U.asTypeOf(sink)) 267 } 268 // only int src need rcTag 269 val rcTagUpdate = fromRenameUpdate.map(x => x.bits.regCacheIdx.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 270 rcTagUpdate.zip(rcTagTable.io.readPorts.map(_.addr)).map(x => x._1 := x._2) 271 val useRegCacheUpdate = fromRenameUpdate.map(x => x.bits.useRegCache.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 272 useRegCacheUpdate.zip(rcTagTable.io.readPorts.map(_.valid)).map(x => x._1 := x._2) 273 rcTagTable.io.readPorts.map(_.ren).zip(readValid).map(x => x._1 := x._2) 274 rcTagTable.io.readPorts.map(_.tag).zip(readAddr).map(x => x._1 := x._2) 275 } 276 }} 277 val allSrcState = Wire(Vec(renameWidth, Vec(numRegSrc, Vec(numRegType, Bool())))) 278 for (i <- 0 until renameWidth){ 279 for (j <- 0 until numRegSrc){ 280 for (k <- 0 until numRegType){ 281 if (!idxRegType(k).contains(j)) { 282 allSrcState(i)(j)(k) := false.B 283 } 284 else { 285 val readidx = i * idxRegType(k).size + idxRegType(k).indexOf(j) 286 val readEn = k match { 287 case 0 => SrcType.isXp(fromRename(i).bits.srcType(j)) 288 case 1 => SrcType.isFp(fromRename(i).bits.srcType(j)) 289 case 2 => SrcType.isVp(fromRename(i).bits.srcType(j)) 290 case 3 => SrcType.isV0(fromRename(i).bits.srcType(j)) 291 case 4 => true.B 292 } 293 allSrcState(i)(j)(k) := readEn && busyTables(k).io.read(readidx).resp || SrcType.isImm(fromRename(i).bits.srcType(j)) 294 } 295 } 296 } 297 } 298 299 300 301 val minIQSelAll = Wire(Vec(needMultiExu.size, Vec(renameWidth, Vec(issueQueueNum, Bool())))) 302 needMultiExu.zipWithIndex.map{ case ((fus, exuidx), needMultiExuidx) => { 303 val suffix = fus.map(_.name).mkString("_") 304 val iqNum = exuidx.size 305 val iqidx = allIssueParams.map(_.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq).zipWithIndex.filter{x => fus.toSet.subsetOf(x._1.toSet)}.map(_._2) 306 println(s"[NewDispatch] ${fus.map(_.name)};iqidx:$iqidx;exuIdx:$exuidx") 307 val compareMatrix = Wire(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"compareMatrix_$suffix") 308 for (i <- 0 until iqNum) { 309 for (j <- 0 until iqNum) { 310 if (i == j) compareMatrix(i)(j) := false.B 311 else if (i < j) compareMatrix(i)(j) := issueQueueCount(exuidx(i)) < issueQueueCount(exuidx(j)) 312 else compareMatrix(i)(j) := !compareMatrix(j)(i) 313 } 314 } 315 val IQSort = Reg(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"IQSort_$suffix}") 316 for (i <- 0 until iqNum){ 317 // i = 0 minimum iq, i = iqNum - 1 -> maximum iq 318 IQSort(i) := compareMatrix.map(x => PopCount(x) === (iqNum - 1 - i).U) 319 } 320 val minIQSel = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))).suggestName(s"minIQSel_$suffix") 321 for (i <- 0 until renameWidth){ 322 val minIQSel_ith = IQSort(i % iqNum) 323 println(s"minIQSel_${i}th_$suffix = IQSort(${i % iqNum})") 324 for (j <- 0 until issueQueueNum){ 325 minIQSel(i)(j) := false.B 326 if (iqidx.contains(j)){ 327 minIQSel(i)(j) := minIQSel_ith(iqidx.indexOf(j)) 328 println(s"minIQSel_${suffix}_${i}_${j} = minIQSel_ith(iqidx.indexOf(${j}))") 329 } 330 } 331 } 332 minIQSelAll(needMultiExuidx) := minIQSel 333 if (backendParams.debugEn){ 334 dontTouch(compareMatrix) 335 dontTouch(IQSort) 336 dontTouch(minIQSel) 337 } 338 } 339 } 340 val fuConfigSeq = needMultiExu.map(_._1) 341 val fuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, Bool()))) 342 fuTypeOH.zip(renameIn).map{ case(oh, in) => { 343 oh := fuConfigSeq.map(x => x.map(xx => in.bits.fuType(xx.fuType.id)).reduce(_ || _) && in.valid) 344 } 345 } 346 // not count itself 347 val popFuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, UInt((renameWidth-1).U.getWidth.W)))) 348 popFuTypeOH.zipWithIndex.map{ case (pop, idx) => { 349 if (idx == 0){ 350 pop := 0.U.asTypeOf(pop) 351 } 352 else { 353 pop.zipWithIndex.map{ case (p, i) => { 354 p := PopCount(fuTypeOH.take(idx).map(x => x(i))) 355 } 356 } 357 } 358 }} 359 val uopSelIQ = Reg(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 360 val fuTypeOHSingle = Wire(Vec(renameWidth, Vec(needSingleIQ.size, Bool()))) 361 fuTypeOHSingle.zip(renameIn).map{ case (oh, in) => { 362 oh := needSingleIQ.map(_._1).map(x => x.map(xx => in.valid && in.bits.fuType(xx.fuType.id)).reduce(_ || _)) 363 }} 364 val uopSelIQSingle = Wire(Vec(needSingleIQ.size, Vec(issueQueueNum, Bool()))) 365 uopSelIQSingle := VecInit(needSingleIQ.map(_._2).flatten.map(x => VecInit((1.U(issueQueueNum.W) << x)(issueQueueNum-1, 0).asBools))) 366 uopSelIQ.zipWithIndex.map{ case (u, i) => { 367 when(io.toRenameAllFire){ 368 u := Mux(renameIn(i).valid, 369 Mux(fuTypeOH(i).asUInt.orR, 370 Mux1H(fuTypeOH(i), minIQSelAll)(Mux1H(fuTypeOH(i), popFuTypeOH(i))), 371 Mux1H(fuTypeOHSingle(i), uopSelIQSingle)), 372 0.U.asTypeOf(u) 373 ) 374 }.elsewhen(io.fromRename(i).fire){ 375 u := 0.U.asTypeOf(u) 376 } 377 }} 378 val uopSelIQMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, UInt(renameWidth.U.getWidth.W)))) 379 uopSelIQMatrix.zipWithIndex.map{ case (u, i) => { 380 u.zipWithIndex.map{ case (uu, j) => { 381 uu := PopCount(uopSelIQ.take(i+1).map(x => x.zipWithIndex.filter(_._2 == j).map(_._1)).flatten) 382 }} 383 }} 384 val IQSelUop = Wire(Vec(IQEnqSum, ValidIO(new DynInst))) 385 val uopBlockByIQ = Wire(Vec(renameWidth, Bool())) 386 val allowDispatch = Wire(Vec(renameWidth, Bool())) 387 val thisCanActualOut = Wire(Vec(renameWidth, Bool())) 388 val lsqCanAccept = Wire(Bool()) 389 for (i <- 0 until RenameWidth){ 390 // update valid logic 391 fromRenameUpdate(i).valid := fromRename(i).valid && allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept && !fromRename(i).bits.eliminatedMove 392 fromRename(i).ready := allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept 393 } 394 var temp = 0 395 allIssueParams.zipWithIndex.map{ case(issue, iqidx) => { 396 for (i <- 0 until issue.numEnq){ 397 val oh = Wire(Vec(renameWidth, Bool())).suggestName(s"oh_IQSelUop_$temp") 398 oh := uopSelIQMatrix.map(_(iqidx)).map(_ === (i+1).U) 399 IQSelUop(temp) := PriorityMux(oh, fromRenameUpdate) 400 // there only assign valid not use PriorityMuxDefalut for better timing 401 IQSelUop(temp).valid := PriorityMuxDefault(oh.zip(fromRenameUpdate.map(_.valid)), false.B) 402 val allFuThisIQ = issue.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq 403 val hasStaFu = !allFuThisIQ.filter(_.name == "sta").isEmpty 404 for (j <- 0 until numRegSrc){ 405 val maskForStd = hasStaFu && (j == 1) 406 val thisSrcHasInt = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) IntRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 407 val thisSrcHasFp = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) FpRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 408 val thisSrcHasVec = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VecRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 409 val thisSrcHasV0 = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) V0RegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 410 val thisSrcHasVl = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VlRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 411 val selSrcState = Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasVl) 412 IQSelUop(temp).bits.srcState(j) := PriorityMux(oh, allSrcState)(j).zip(selSrcState).filter(_._2 == true).map(_._1).foldLeft(false.B)(_ || _).asUInt 413 } 414 temp = temp + 1 415 if (backendParams.debugEn){ 416 dontTouch(oh) 417 } 418 } 419 }} 420 temp = 0 421 val uopBlockMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 422 val uopBlockMatrixForAssign = allIssueParams.zipWithIndex.map { case (issue, iqidx) => { 423 val result = uopSelIQMatrix.map(_(iqidx)).map(x => Mux(io.toIssueQueues(temp).ready, x > issue.numEnq.U, x.orR)) 424 temp = temp + issue.numEnq 425 result 426 }}.transpose 427 uopBlockMatrix.zip(uopBlockMatrixForAssign).map(x => x._1 := VecInit(x._2)) 428 uopBlockByIQ := uopBlockMatrix.map(_.reduce(_ || _)) 429 io.toIssueQueues.zip(IQSelUop).map(x => { 430 x._1.valid := x._2.valid 431 x._1.bits := x._2.bits 432 }) 433 if (backendParams.debugEn){ 434 dontTouch(uopSelIQMatrix) 435 dontTouch(IQSelUop) 436 dontTouch(fromRenameUpdate) 437 dontTouch(uopBlockByIQ) 438 dontTouch(allowDispatch) 439 dontTouch(thisCanActualOut) 440 dontTouch(popFuTypeOH) 441 dontTouch(fuTypeOH) 442 dontTouch(fuTypeOHSingle) 443 dontTouch(minIQSelAll) 444 } 445 /////////////////////////////////////////////////////////// 446 447 val lsqEnqCtrl = Module(new LsqEnqCtrl) 448 449 // TODO: check lsqEnqCtrl redirect logic 450 // here is RegNext because dispatch2iq use s2_s4_redirect, newDispatch use s1_s3_redirect 451 lsqEnqCtrl.io.redirect := RegNext(io.redirect) 452 lsqEnqCtrl.io.lcommit := io.fromMem.lcommit 453 lsqEnqCtrl.io.scommit := io.fromMem.scommit 454 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.lqCancelCnt 455 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.sqCancelCnt 456 lsqEnqCtrl.io.enq.iqAccept := io.fromRename.map(x => !x.valid || x.fire) 457 io.toMem.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 458 459 private val enqLsqIO = lsqEnqCtrl.io.enq 460 private val lqFreeCount = lsqEnqCtrl.io.lqFreeCount 461 private val sqFreeCount = lsqEnqCtrl.io.sqFreeCount 462 463 private val numLoadDeq = LSQLdEnqWidth 464 private val numStoreAMODeq = LSQStEnqWidth 465 private val numVLoadDeq = LoadPipelineWidth 466 private val numDeq = enqLsqIO.req.size 467 lsqCanAccept := enqLsqIO.canAccept 468 469 private val isLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isLoad(x.bits.fuType))) 470 private val isStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isStore(x.bits.fuType))) 471 private val isAMOVec = fromRename.map(x => x.valid && FuType.isAMO(x.bits.fuType)) 472 private val isStoreAMOVec = fromRename.map(x => x.valid && (FuType.isStore(x.bits.fuType) || FuType.isAMO(x.bits.fuType))) 473 private val isVLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isVLoad(x.bits.fuType))) 474 private val isVStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isVStore(x.bits.fuType))) 475 476 private val loadCntVec = VecInit(isLoadVec.indices.map(x => PopCount(isLoadVec.slice(0, x + 1)))) 477 private val storeAMOCntVec = VecInit(isStoreAMOVec.indices.map(x => PopCount(isStoreAMOVec.slice(0, x + 1)))) 478 private val vloadCntVec = VecInit(isVLoadVec.indices.map(x => PopCount(isVLoadVec.slice(0, x + 1)))) 479 480 private val s0_enqLsq_resp = Wire(enqLsqIO.resp.cloneType) 481 for (i <- 0 until RenameWidth) { 482 // update lqIdx sqIdx 483 fromRenameUpdate(i).bits.lqIdx := s0_enqLsq_resp(i).lqIdx 484 fromRenameUpdate(i).bits.sqIdx := s0_enqLsq_resp(i).sqIdx 485 } 486 487 val loadBlockVec = VecInit(loadCntVec.map(_ > numLoadDeq.U)) 488 val storeAMOBlockVec = VecInit(storeAMOCntVec.map(_ > numStoreAMODeq.U)) 489 val vloadBlockVec = VecInit(vloadCntVec.map(_ > numVLoadDeq.U)) 490 val lsStructBlockVec = VecInit((loadBlockVec.zip(storeAMOBlockVec)).zip(vloadBlockVec).map(x => x._1._1 || x._1._2 || x._2)) 491 if (backendParams.debugEn) { 492 dontTouch(loadBlockVec) 493 dontTouch(storeAMOBlockVec) 494 dontTouch(lsStructBlockVec) 495 dontTouch(vloadBlockVec) 496 dontTouch(isLoadVec) 497 dontTouch(isVLoadVec) 498 dontTouch(loadCntVec) 499 } 500 501 private val uop = fromRename.map(_.bits) 502 private val fuType = uop.map(_.fuType) 503 private val fuOpType = uop.map(_.fuOpType) 504 private val vtype = uop.map(_.vpu.vtype) 505 private val sew = vtype.map(_.vsew) 506 private val lmul = vtype.map(_.vlmul) 507 private val eew = uop.map(_.vpu.veew) 508 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 509 private val nf = fuOpType.zip(uop.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 510 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 511 Mux( 512 LSUOpType.isWhole(fuOpTypeItem), 513 GenUSWholeEmul(nf(index)), 514 Mux( 515 LSUOpType.isMasked(fuOpTypeItem), 516 0.U(mulBits.W), 517 EewLog2(eew(index)) - sew(index) + lmul(index) 518 ) 519 ) 520 } 521 522 private val isVlsType = fuType.map(fuTypeItem => FuType.isVls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 523 private val isSegment = fuType.map(fuTypeItem => FuType.isVsegls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 524 // TODO 525 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 526 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 527 isVlsTypeItme && isUnitStrideItem 528 } 529 private val isfofFixVlUop = uop.map { x => x.vpu.isVleff && x.lastUop } 530 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 531 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 532 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 533 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 534 private val numLsElem = VecInit(uop.map(_.numLsElem)) 535 536 // The maximum 'numLsElem' number that can be emitted per port is: 537 // 16 2 2 2 2 2. 538 // The 'allowDispatch' calculations are done conservatively for timing purposes: 539 // The Flow of scalar instructions is considered 1, 540 // The flow of vector 'unit-stride' instructions is considered 2, and the flow of other vector instructions is considered 16. 541 private val conserveFlows = isVlsType.zipWithIndex.map { case (isVlsTyepItem, index) => 542 Mux( 543 isVlsTyepItem, 544 if (index == 0) Mux(isUnitStride(index), VecMemUnitStrideMaxFlowNum.U, 16.U) else VecMemUnitStrideMaxFlowNum.U, 545 1.U 546 ) 547 } 548 549 // A conservative allocation strategy is adopted here. 550 // Vector 'unit-stride' instructions and scalar instructions can be issued from all six ports, 551 // while other vector instructions can only be issued from the first port 552 // if is segment instruction, need disptch it to Vldst_RS0, so, except port 0, stall other. 553 // The allocation needs to meet a few conditions: 554 // 1) The lsq has enough entris. 555 // 2) The number of flows accumulated does not exceed VecMemDispatchMaxNumber. 556 // 3) Vector instructions other than 'unit-stride' can only be issued on the first port. 557 558 559 for (index <- allowDispatch.indices) { 560 val flowTotal = Wire(UInt(log2Up(VirtualLoadQueueMaxStoreQueueSize + 1).W)) 561 flowTotal := conserveFlows.take(index + 1).reduce(_ +& _) 562 if (index == 0) { 563 when(isStoreVec(index) || isVStoreVec(index)) { 564 allowDispatch(index) := sqFreeCount > flowTotal 565 }.elsewhen(isLoadVec(index) || isVLoadVec(index)) { 566 allowDispatch(index) := lqFreeCount > flowTotal 567 }.elsewhen(isAMOVec(index)) { 568 allowDispatch(index) := true.B 569 }.otherwise { 570 allowDispatch(index) := true.B 571 } 572 } 573 else { 574 when(isStoreVec(index) || isVStoreVec(index)) { 575 allowDispatch(index) := (sqFreeCount > flowTotal) && (isVecUnitType(index) || !isVlsType(index)) && allowDispatch(index - 1) 576 }.elsewhen(isLoadVec(index) || isVLoadVec(index)) { 577 allowDispatch(index) := (lqFreeCount > flowTotal) && (isVecUnitType(index) || !isVlsType(index)) && allowDispatch(index - 1) 578 }.elsewhen(isAMOVec(index)) { 579 allowDispatch(index) := allowDispatch(index - 1) 580 }.otherwise { 581 allowDispatch(index) := allowDispatch(index - 1) 582 } 583 } 584 } 585 586 587 // enqLsq io 588 require(enqLsqIO.req.size == enqLsqIO.resp.size) 589 for (i <- enqLsqIO.req.indices) { 590 when(!io.fromRename(i).fire) { 591 enqLsqIO.needAlloc(i) := 0.U 592 }.elsewhen(isStoreVec(i) || isVStoreVec(i)) { 593 enqLsqIO.needAlloc(i) := 2.U // store | vstore 594 }.elsewhen(isLoadVec(i) || isVLoadVec(i)){ 595 enqLsqIO.needAlloc(i) := 1.U // load | vload 596 }.otherwise { 597 enqLsqIO.needAlloc(i) := 0.U 598 } 599 enqLsqIO.req(i).valid := io.fromRename(i).fire && !isAMOVec(i) && !isSegment(i) && !isfofFixVlUop(i) 600 enqLsqIO.req(i).bits := io.fromRename(i).bits 601 602 // This is to make it easier to calculate in LSQ. 603 // Both scalar instructions and vector instructions with FLOW equal to 1 have a NUM value of 1.” 604 // But, the 'numLsElem' that is not a vector is set to 0 when passed to IQ 605 enqLsqIO.req(i).bits.numLsElem := Mux(isVlsType(i), numLsElem(i), 1.U) 606 s0_enqLsq_resp(i) := enqLsqIO.resp(i) 607 } 608 609 610 611 612 613 614 615 616 617 618 619 620 val isFp = VecInit(fromRename.map(req => FuType.isFArith(req.bits.fuType))) 621 val isVec = VecInit(fromRename.map(req => FuType.isVArith (req.bits.fuType) || 622 FuType.isVsetRvfWvf(req.bits.fuType))) 623 val isMem = VecInit(fromRename.map(req => FuType.isMem(req.bits.fuType) || 624 FuType.isVls (req.bits.fuType))) 625 val isLs = VecInit(fromRename.map(req => FuType.isLoadStore(req.bits.fuType))) 626 val isVls = VecInit(fromRename.map(req => FuType.isVls (req.bits.fuType))) 627 val isStore = VecInit(fromRename.map(req => FuType.isStore(req.bits.fuType))) 628 val isVStore = VecInit(fromRename.map(req => FuType.isVStore(req.bits.fuType))) 629 val isAMO = VecInit(fromRename.map(req => FuType.isAMO(req.bits.fuType))) 630 val isBlockBackward = VecInit(fromRename.map(x => x.valid && x.bits.blockBackward)) 631 val isWaitForward = VecInit(fromRename.map(x => x.valid && x.bits.waitForward)) 632 633 // Singlestep should only commit one machine instruction after dret, and then hart enter debugMode according to singlestep exception. 634 val s_holdRobidx :: s_updateRobidx :: Nil = Enum(2) 635 val singleStepState = RegInit(s_updateRobidx) 636 637 val robidxStepNext = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 638 val robidxStepReg = RegInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 639 val robidxCanCommitStepping = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 640 641 when(!io.singleStep) { 642 singleStepState := s_updateRobidx 643 }.elsewhen(io.singleStep && fromRename(0).fire && io.enqRob.req(0).valid) { 644 singleStepState := s_holdRobidx 645 robidxStepNext := fromRename(0).bits.robIdx 646 } 647 648 when(singleStepState === s_updateRobidx) { 649 robidxStepReg := robidxStepNext 650 robidxCanCommitStepping := robidxStepNext 651 }.elsewhen(singleStepState === s_holdRobidx) { 652 robidxStepReg := robidxStepReg 653 robidxCanCommitStepping := robidxStepReg 654 } 655 656 val updatedUop = Wire(Vec(RenameWidth, new DynInst)) 657 val checkpoint_id = RegInit(0.U(64.W)) 658 checkpoint_id := checkpoint_id + PopCount((0 until RenameWidth).map(i => 659 fromRename(i).fire 660 )) 661 662 663 for (i <- 0 until RenameWidth) { 664 665 updatedUop(i) := fromRename(i).bits 666 updatedUop(i).debugInfo.eliminatedMove := fromRename(i).bits.eliminatedMove 667 // For the LUI instruction: psrc(0) is from register file and should always be zero. 668 when (fromRename(i).bits.isLUI) { 669 updatedUop(i).psrc(0) := 0.U 670 } 671 //TODO: vec ls mdp 672 io.lfst.req(i).valid := fromRename(i).fire && updatedUop(i).storeSetHit 673 io.lfst.req(i).bits.isstore := isStore(i) 674 io.lfst.req(i).bits.ssid := updatedUop(i).ssid 675 io.lfst.req(i).bits.robIdx := updatedUop(i).robIdx // speculatively assigned in rename 676 677 // override load delay ctrl signal with store set result 678 if(StoreSetEnable) { 679 updatedUop(i).loadWaitBit := io.lfst.resp(i).bits.shouldWait 680 updatedUop(i).waitForRobIdx := io.lfst.resp(i).bits.robIdx 681 } else { 682 updatedUop(i).loadWaitBit := isLs(i) && !isStore(i) && fromRename(i).bits.loadWaitBit 683 } 684 // // update singleStep, singleStep exception only enable in next machine instruction. 685 updatedUop(i).singleStep := io.singleStep && (fromRename(i).bits.robIdx =/= robidxCanCommitStepping) 686 when (fromRename(i).fire) { 687 XSDebug(TriggerAction.isDmode(updatedUop(i).trigger) || updatedUop(i).exceptionVec(breakPoint), s"Debug Mode: inst ${i} has frontend trigger exception\n") 688 XSDebug(updatedUop(i).singleStep, s"Debug Mode: inst ${i} has single step exception\n") 689 } 690 if (env.EnableDifftest) { 691 // debug runahead hint 692 val debug_runahead_checkpoint_id = Wire(checkpoint_id.cloneType) 693 if(i == 0){ 694 debug_runahead_checkpoint_id := checkpoint_id 695 } else { 696 debug_runahead_checkpoint_id := checkpoint_id + PopCount((0 until i).map(i => 697 fromRename(i).fire 698 )) 699 } 700 } 701 } 702 703 // store set perf count 704 XSPerfAccumulate("waittable_load_wait", PopCount((0 until RenameWidth).map(i => 705 fromRename(i).fire && fromRename(i).bits.loadWaitBit && !isStore(i) && isLs(i) 706 ))) 707 XSPerfAccumulate("storeset_load_wait", PopCount((0 until RenameWidth).map(i => 708 fromRename(i).fire && updatedUop(i).loadWaitBit && !isStore(i) && isLs(i) 709 ))) 710 XSPerfAccumulate("storeset_load_strict_wait", PopCount((0 until RenameWidth).map(i => 711 fromRename(i).fire && updatedUop(i).loadWaitBit && updatedUop(i).loadWaitStrict && !isStore(i) && isLs(i) 712 ))) 713 XSPerfAccumulate("storeset_store_wait", PopCount((0 until RenameWidth).map(i => 714 fromRename(i).fire && updatedUop(i).loadWaitBit && isStore(i) 715 ))) 716 717 val allResourceReady = io.enqRob.canAccept 718 719 // Instructions should enter dispatch queues in order. 720 // blockedByWaitForward: this instruction is blocked by itself (based on waitForward) 721 // nextCanOut: next instructions can out (based on blockBackward) 722 // notBlockedByPrevious: previous instructions can enqueue 723 val hasException = VecInit(fromRename.zip(updatedUop).map { 724 case (fromRename: DecoupledIO[DynInst], uop: DynInst) => 725 fromRename.bits.hasException || uop.singleStep 726 }) 727 728 private val blockedByWaitForward = Wire(Vec(RenameWidth, Bool())) 729 blockedByWaitForward(0) := !io.enqRob.isEmpty && isWaitForward(0) 730 for (i <- 1 until RenameWidth) { 731 blockedByWaitForward(i) := blockedByWaitForward(i - 1) || (!io.enqRob.isEmpty || Cat(fromRename.take(i).map(_.valid)).orR) && isWaitForward(i) 732 } 733 if(backendParams.debugEn){ 734 dontTouch(blockedByWaitForward) 735 } 736 737 // Only the uop with block backward flag will block the next uop 738 val nextCanOut = VecInit((0 until RenameWidth).map(i => 739 !isBlockBackward(i) 740 )) 741 val notBlockedByPrevious = VecInit((0 until RenameWidth).map(i => 742 if (i == 0) true.B 743 else Cat((0 until i).map(j => nextCanOut(j))).andR 744 )) 745 746 // for noSpecExec: (robEmpty || !this.noSpecExec) && !previous.noSpecExec 747 // For blockBackward: 748 // this instruction can actually dequeue: 3 conditions 749 // (1) resources are ready 750 // (2) previous instructions are ready 751 thisCanActualOut := VecInit((0 until RenameWidth).map(i => !blockedByWaitForward(i) && notBlockedByPrevious(i) && io.enqRob.canAccept)) 752 val thisActualOut = (0 until RenameWidth).map(i => io.enqRob.req(i).valid && io.enqRob.canAccept) 753 val hasValidException = fromRename.zip(hasException).map(x => x._1.valid && x._2) 754 755 // input for ROB, LSQ 756 for (i <- 0 until RenameWidth) { 757 // needAlloc no use, need deleted 758 io.enqRob.needAlloc(i) := fromRename(i).valid 759 io.enqRob.req(i).valid := fromRename(i).fire 760 io.enqRob.req(i).bits := updatedUop(i) 761 io.enqRob.req(i).bits.hasException := updatedUop(i).hasException || updatedUop(i).singleStep 762 io.enqRob.req(i).bits.numWB := Mux(updatedUop(i).singleStep, 0.U, updatedUop(i).numWB) 763 } 764 765 val hasValidInstr = VecInit(fromRename.map(_.valid)).asUInt.orR 766 val hasSpecialInstr = Cat((0 until RenameWidth).map(i => isBlockBackward(i))).orR 767 768 private val canAccept = !hasValidInstr || !hasSpecialInstr && io.enqRob.canAccept 769 770 val isWaitForwardOrBlockBackward = isWaitForward.asUInt.orR || isBlockBackward.asUInt.orR 771 val renameFireCnt = PopCount(fromRename.map(_.fire)) 772 773 val stall_rob = hasValidInstr && !io.enqRob.canAccept 774 val stall_int_dq = hasValidInstr && io.enqRob.canAccept 775 val stall_int_dq0 = hasValidInstr && io.enqRob.canAccept 776 val stall_int_dq1 = hasValidInstr && io.enqRob.canAccept 777 val stall_fp_dq = hasValidInstr && io.enqRob.canAccept 778 val stall_ls_dq = hasValidInstr && io.enqRob.canAccept 779 780 XSPerfAccumulate("in_valid_count", PopCount(fromRename.map(_.valid))) 781 XSPerfAccumulate("in_fire_count", PopCount(fromRename.map(_.fire))) 782 XSPerfAccumulate("in_valid_not_ready_count", PopCount(fromRename.map(x => x.valid && !x.ready))) 783 XSPerfAccumulate("wait_cycle", !fromRename.head.valid && allResourceReady) 784 785 XSPerfAccumulate("stall_cycle_rob", stall_rob) 786 XSPerfAccumulate("stall_cycle_int_dq0", stall_int_dq0) 787 XSPerfAccumulate("stall_cycle_int_dq1", stall_int_dq1) 788 XSPerfAccumulate("stall_cycle_fp_dq", stall_fp_dq) 789 XSPerfAccumulate("stall_cycle_ls_dq", stall_ls_dq) 790 791 val notIssue = !io.debugTopDown.fromRob.robHeadLsIssue 792 val tlbReplay = io.debugTopDown.fromCore.fromMem.robHeadTlbReplay 793 val tlbMiss = io.debugTopDown.fromCore.fromMem.robHeadTlbMiss 794 val vioReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadVio 795 val mshrReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadMSHR 796 val l1Miss = io.debugTopDown.fromCore.fromMem.robHeadMissInDCache 797 val l2Miss = io.debugTopDown.fromCore.l2MissMatch 798 val l3Miss = io.debugTopDown.fromCore.l3MissMatch 799 800 val ldReason = Mux(l3Miss, TopDownCounters.LoadMemStall.id.U, 801 Mux(l2Miss, TopDownCounters.LoadL3Stall.id.U, 802 Mux(l1Miss, TopDownCounters.LoadL2Stall.id.U, 803 Mux(notIssue, TopDownCounters.MemNotReadyStall.id.U, 804 Mux(tlbMiss, TopDownCounters.LoadTLBStall.id.U, 805 Mux(tlbReplay, TopDownCounters.LoadTLBStall.id.U, 806 Mux(mshrReplay, TopDownCounters.LoadMSHRReplayStall.id.U, 807 Mux(vioReplay, TopDownCounters.LoadVioReplayStall.id.U, 808 TopDownCounters.LoadL1Stall.id.U)))))))) 809 810 val decodeReason = RegNextN(io.stallReason.reason, 2) 811 val renameReason = RegNext(io.stallReason.reason) 812 813 val stallReason = Wire(chiselTypeOf(io.stallReason.reason)) 814 val firedVec = fromRename.map(_.fire) 815 io.stallReason.backReason.valid := !canAccept 816 io.stallReason.backReason.bits := TopDownCounters.OtherCoreStall.id.U 817 stallReason.zip(io.stallReason.reason).zip(firedVec).zipWithIndex.map { case (((update, in), fire), idx) => 818 val headIsInt = FuType.isInt(io.robHead.getDebugFuType) && io.robHeadNotReady 819 val headIsFp = FuType.isFArith(io.robHead.getDebugFuType) && io.robHeadNotReady 820 val headIsDiv = FuType.isDivSqrt(io.robHead.getDebugFuType) && io.robHeadNotReady 821 val headIsLd = io.robHead.getDebugFuType === FuType.ldu.U && io.robHeadNotReady || !io.lqCanAccept 822 val headIsSt = io.robHead.getDebugFuType === FuType.stu.U && io.robHeadNotReady || !io.sqCanAccept 823 val headIsAmo = io.robHead.getDebugFuType === FuType.mou.U && io.robHeadNotReady 824 val headIsLs = headIsLd || headIsSt 825 val robLsFull = io.robFull || !io.lqCanAccept || !io.sqCanAccept 826 827 import TopDownCounters._ 828 update := MuxCase(OtherCoreStall.id.U, Seq( 829 // fire 830 (fire ) -> NoStall.id.U , 831 // dispatch not stall / core stall from decode or rename 832 (in =/= OtherCoreStall.id.U && in =/= NoStall.id.U ) -> in , 833 // rob stall 834 (headIsAmo ) -> AtomicStall.id.U , 835 (headIsSt ) -> StoreStall.id.U , 836 (headIsLd ) -> ldReason , 837 (headIsDiv ) -> DivStall.id.U , 838 (headIsInt ) -> IntNotReadyStall.id.U , 839 (headIsFp ) -> FPNotReadyStall.id.U , 840 (renameReason(idx) =/= NoStall.id.U ) -> renameReason(idx) , 841 (decodeReason(idx) =/= NoStall.id.U ) -> decodeReason(idx) , 842 )) 843 } 844 845 TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)))) 846 847 val robTrueCommit = io.debugTopDown.fromRob.robTrueCommit 848 TopDownCounters.values.foreach(ctr => XSPerfRolling("td_"+ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)), 849 robTrueCommit, 1000, clock, reset)) 850 851 XSPerfHistogram("slots_fire", PopCount(thisActualOut), true.B, 0, RenameWidth+1, 1) 852 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 853 XSPerfHistogram("slots_valid_pure", PopCount(io.enqRob.req.map(_.valid)), thisActualOut(0), 0, RenameWidth+1, 1) 854 XSPerfHistogram("slots_valid_rough", PopCount(io.enqRob.req.map(_.valid)), true.B, 0, RenameWidth+1, 1) 855 856 val perfEvents = Seq( 857 ("dispatch_in", PopCount(fromRename.map(_.valid && fromRename(0).ready)) ), 858 ("dispatch_empty", !hasValidInstr ), 859 ("dispatch_utili", PopCount(fromRename.map(_.valid)) ), 860 ("dispatch_waitinstr", PopCount(fromRename.map(!_.valid && canAccept)) ), 861 ("dispatch_stall_cycle_lsq", false.B ), 862 ("dispatch_stall_cycle_rob", stall_rob ), 863 ("dispatch_stall_cycle_int_dq", stall_int_dq ), 864 ("dispatch_stall_cycle_fp_dq", stall_fp_dq ), 865 ("dispatch_stall_cycle_ls_dq", stall_ls_dq ) 866 ) 867 generatePerfEvent() 868} 869