xref: /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1package xiangshan.backend.decode.isa.bitfield
2
3import chisel3._
4
5abstract class RiscvInst(bitWidth: Int) extends Bundle {
6  val inst: UInt = UInt(bitWidth.W)
7}
8
9class Riscv32BitInst extends RiscvInst(32) {
10  def ALL     : UInt  = inst
11  def OPCODE  : UInt  = inst( 6,  0)
12  def RD      : UInt  = inst(11,  7)
13  def FUNCT3  : UInt  = inst(14, 12)
14  def RS1     : UInt  = inst(19, 15)
15  def RS2     : UInt  = inst(24, 20)
16  def FUNCT7  : UInt  = inst(31, 25)
17}
18
19trait BitFieldsI { this: Riscv32BitInst =>
20  def IMM12   : UInt  = inst(31, 20)
21  def SHAMT6  : UInt  = inst(25, 20)
22  def SHAMT5  : UInt  = inst(24, 20)
23}
24
25trait BitFieldsS { this: Riscv32BitInst =>
26  def IMM5    : UInt  = inst(11,  7)
27  def IMM7    : UInt  = inst(31, 25)
28}
29
30trait BitFieldsCSR { this: Riscv32BitInst =>
31  def CSRIDX  : UInt  = inst(31, 20)
32  def CSRIMM  : UInt  = inst(19, 15)
33}
34
35trait BitFieldsFp { this: Riscv32BitInst =>
36  def FD      : UInt  = inst(11,  7)
37  def FS1     : UInt  = inst(19, 15)
38  def FS2     : UInt  = inst(24, 20)
39  def FS3     : UInt  = inst(31, 27)
40  def RM      : UInt  = inst(14, 12) // round mode
41  def CONV_SGN: UInt  = inst(24, 20)
42  def FMT     : UInt  = inst(26, 25)
43  def TYP     : UInt  = inst(21, 20)
44}
45
46trait BitFieldsVec { this: Riscv32BitInst =>
47  def VCATEGORY     : UInt  = inst(14, 12)
48  def NF            : UInt  = inst(31, 29)
49  def MEW           : UInt  = inst(28)
50  def MOP           : UInt  = inst(27, 26)
51  def VM            : UInt  = inst(25)
52  def LUMOP         : UInt  = inst(24, 20)
53  def SUMOP         : UInt  = inst(24, 20)
54  def WIDTH         : UInt  = inst(14, 12)
55  def VD            : UInt  = inst(11,  7)
56  def VS1           : UInt  = inst(19, 15)
57  def VS2           : UInt  = inst(24, 20)
58  def VS3           : UInt  = inst(11,  7)
59  def FUNCT6        : UInt  = inst(31 ,26)
60  def ZIMM_VSETVLI  : UInt  = inst(30, 20)
61  def ZIMM_VSETIVLI : UInt  = inst(29, 20)
62  def UIMM_VSETIVLI : UInt  = inst(19, 15)
63  def IMM5_OPIVI    : UInt  = inst(19, 15)
64
65  def getInstVType : InstVType = {
66    val res = Wire(new InstVType)
67    res.vlmul := ZIMM_VSETVLI(2, 0)
68    res.vsew  := ZIMM_VSETVLI(5, 3)
69    res.vta   := ZIMM_VSETVLI(6)
70    res.vma   := ZIMM_VSETVLI(7)
71    res
72  }
73
74  def isVecStore = {
75    this.OPCODE === "b0100111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B)
76  }
77
78  def isVecLoad = {
79    this.OPCODE === "b0000111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B)
80  }
81}
82
83class XSInstBitFields extends Riscv32BitInst
84  with BitFieldsI
85  with BitFieldsS
86  with BitFieldsCSR
87  with BitFieldsFp
88  with BitFieldsVec
89
90class InstVType extends Bundle {
91  val reserved = UInt(3.W)
92  val vma = Bool()
93  val vta = Bool()
94  val vsew = UInt(3.W)
95  val vlmul = UInt(3.W)
96}
97
98