1package xiangshan.backend.decode.isa.bitfield 2 3import chisel3._ 4 5abstract class RiscvInst(bitWidth: Int) extends Bundle { 6 val inst: UInt = UInt(bitWidth.W) 7} 8 9class Riscv32BitInst extends RiscvInst(32) { 10 def ALL : UInt = inst 11 def OPCODE : UInt = inst( 6, 0) 12 def RD : UInt = inst(11, 7) 13 def FUNCT3 : UInt = inst(14, 12) 14 def RS1 : UInt = inst(19, 15) 15 def RS2 : UInt = inst(24, 20) 16 def FUNCT7 : UInt = inst(31, 25) 17 def OPCODE5Bit: UInt = inst( 6, 2) 18 def OPCODE7Bit: UInt = inst( 6, 0) 19} 20 21trait BitFieldsI { this: Riscv32BitInst => 22 def IMM12 : UInt = inst(31, 20) 23 def SHAMT6 : UInt = inst(25, 20) 24 def SHAMT5 : UInt = inst(24, 20) 25} 26 27trait BitFieldsS { this: Riscv32BitInst => 28 def IMM5 : UInt = inst(11, 7) 29 def IMM7 : UInt = inst(31, 25) 30} 31 32trait BitFieldsCSR { this: Riscv32BitInst => 33 def CSRIDX : UInt = inst(31, 20) 34 def CSRIMM : UInt = inst(19, 15) 35} 36 37trait BitFieldsFp { this: Riscv32BitInst => 38 def FD : UInt = inst(11, 7) 39 def FS1 : UInt = inst(19, 15) 40 def FS2 : UInt = inst(24, 20) 41 def FS3 : UInt = inst(31, 27) 42 def RM : UInt = inst(14, 12) // round mode 43 def CONV_SGN: UInt = inst(24, 20) 44 def FMT : UInt = inst(26, 25) 45 def TYP : UInt = inst(21, 20) 46} 47 48trait BitFieldsVec { this: Riscv32BitInst => 49 def VCATEGORY : UInt = inst(14, 12) 50 def NF : UInt = inst(31, 29) 51 def MEW : UInt = inst(28) 52 def MOP : UInt = inst(27, 26) 53 def VM : UInt = inst(25) 54 def LUMOP : UInt = inst(24, 20) 55 def SUMOP : UInt = inst(24, 20) 56 def WIDTH : UInt = inst(14, 12) 57 def VD : UInt = inst(11, 7) 58 def VS1 : UInt = inst(19, 15) 59 def VS2 : UInt = inst(24, 20) 60 def VS3 : UInt = inst(11, 7) 61 def FUNCT6 : UInt = inst(31 ,26) 62 def ZIMM_VSETVLI : UInt = inst(30, 20) 63 def ZIMM_VSETIVLI : UInt = inst(29, 20) 64 def UIMM_VSETIVLI : UInt = inst(19, 15) 65 def IMM5_OPIVI : UInt = inst(19, 15) 66 67 def getInstVType : InstVType = { 68 val res = Wire(new InstVType) 69 res.vlmul := ZIMM_VSETVLI(2, 0) 70 res.vsew := ZIMM_VSETVLI(5, 3) 71 res.vta := ZIMM_VSETVLI(6) 72 res.vma := ZIMM_VSETVLI(7) 73 res 74 } 75 76 def isVecStore = { 77 this.OPCODE === "b0100111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B) 78 } 79 80 def isVecLoad = { 81 this.OPCODE === "b0000111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B) 82 } 83} 84 85class XSInstBitFields extends Riscv32BitInst 86 with BitFieldsI 87 with BitFieldsS 88 with BitFieldsCSR 89 with BitFieldsFp 90 with BitFieldsVec 91 92class InstVType extends Bundle { 93 val reserved = UInt(3.W) 94 val vma = Bool() 95 val vta = Bool() 96 val vsew = UInt(3.W) 97 val vlmul = UInt(3.W) 98} 99 100object OPCODE5Bit { 101 val LOAD = "b00_000".U 102 val LOAD_FP = "b00_001".U 103 val CUSTOM_0 = "b00_010".U 104 val MSIC_MEM = "b00_011".U 105 val OP_IMM = "b00_100".U 106 val AUIPC = "b00_101".U 107 val OP_IMM_32 = "b00_110".U 108 val INST48b_0 = "b00_111".U 109 110 val STORE = "b01_000".U 111 val STORE_FP = "b01_001".U 112 val CUSTOM_1 = "b01_010".U 113 val AMO = "b01_011".U 114 val OP = "b01_100".U 115 val LUI = "b01_101".U 116 val OP_32 = "b01_110".U 117 val INST64b = "b01_111".U 118 119 val MADD = "b10_000".U 120 val MSUB = "b10_001".U 121 val NMSUB = "b10_010".U 122 val NMADD = "b10_011".U 123 val OP_FP = "b10_100".U 124 val OP_V = "b10_101".U 125 val CUSTOM_2 = "b10_110".U 126 val INST48b_1 = "b10_111".U 127 128 val BRANCH = "b11_000".U 129 val JALR = "b11_001".U 130 val RESERVED_0 = "b11_010".U 131 val JAL = "b11_011".U 132 val SYSTEM = "b11_100".U 133 val RESERVED_1 = "b11_101".U 134 val CUSTOM_3 = "b11_110".U 135 val INSTge80b = "b11_111".U 136} 137 138object OPCODE7Bit { 139 val VECTOR_ARITH = "b1010111".U 140} 141