1package xiangshan.backend.decode 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import freechips.rocketchip.util.uintToBitPat 8import freechips.rocketchip.rocket.Instructions._ 9import utils._ 10import xiangshan.ExceptionNO.illegalInstr 11import xiangshan._ 12import yunsuan.{VfpuType, VipuType} 13 14abstract class VecType { 15 def X = BitPat("b?") 16 def N = BitPat("b0") 17 def Y = BitPat("b1") 18 def generate() : List[BitPat] 19 def asOldDecodeOutput(): List[BitPat] = { 20 val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 21 List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm) 22 } 23 def asFirstStageDecodeOutput(): List[BitPat] = { 24 val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 25 List (src1, src2, src3, fu, fuOp, xWen, fWen, bitPatToUInt(vWen) | bitPatToUInt(mWen), xsTrap, noSpec, blockBack, flushPipe, selImm) 26 } 27} 28 29case class OPIVV(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 30 def generate() : List[BitPat] = { 31 // xsTrap 32 // | noSpec 33 // xWen | | blockBack 34 // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 35 List (SrcType.vp, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 36 } 37} 38 39case class OPIVX(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 40 def generate() : List[BitPat] = { 41 // xsTrap 42 // | noSpec 43 // xWen | | blockBack 44 // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 45 List (SrcType.xp, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 46 } 47} 48 49case class OPIVI(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean, selImm: BitPat) extends VecType { 50 def generate() : List[BitPat] = { 51 // xsTrap 52 // | noSpec 53 // xWen | | blockBack 54 // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 55 List (SrcType.imm, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, selImm) 56 } 57} 58 59case class OPMVV(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 60 private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 61 def generate() : List[BitPat] = { 62 val vxsatWen = false 63 // xsTrap 64 // | noSpec 65 // xWen fWen | | blockBack 66 // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 67 List (SrcType.vp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 68 } 69} 70 71case class OPMVX(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 72 private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 73 def generate() : List[BitPat] = { 74 val vxsatWen = false 75 // xsTrap 76 // | noSpec 77 // xWen fWen | | blockBack 78 // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 79 List (SrcType.xp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 80 } 81} 82 83case class OPFVV(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 84 def generate() : List[BitPat] = { 85 val vxsatWen = false 86 // xsTrap 87 // | noSpec 88 // xWen fWen | | blockBack 89 // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 90 List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 91 } 92} 93 94case class OPFVF(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 95 def generate() : List[BitPat] = { 96 val vxsatWen = false 97 // xsTrap 98 // | noSpec 99 // xWen fWen | | blockBack 100 // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 101 List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 102 } 103} 104 105case class VSET(vli: Boolean, vtypei: Boolean, fuOp: BitPat, flushPipe: Boolean, selImm: BitPat) extends VecType { 106 def generate() : List[BitPat] = { 107 val src1 = if (vli) SrcType.imm else SrcType.xp 108 val src2 = if (vtypei) SrcType.imm else SrcType.xp 109 // xWen 110 // | fWen xsTrap 111 // | | vWen | noSpec 112 // | | | mWen | | blockBack 113 // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 114 List (src1, src2, SrcType.X, FuType.alu, fuOp, Y, N, N, N, N, N, N, N, Y, selImm) 115 } 116} 117 118case class VLD(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, ff: Boolean = false, 119 mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends VecType { 120 def generate() : List[BitPat] = { 121 val fu = FuType.vldu 122 val src1 = SrcType.xp 123 val src3 = SrcType.X 124 // xWen 125 // | fWen xsTrap 126 // | | vWen | noSpec 127 // | | | mWen | | blockBack 128 // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 129 List (src1, src2, src3, fu, fuOp, N, N, Y, N, N, N, N, N, Y, SelImm.X) 130 } 131} 132 133case class VST(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, 134 mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends VecType { 135 def generate() : List[BitPat] = { 136 val fu = FuType.vstu 137 val src1 = SrcType.xp 138 val src3 = SrcType.vp 139 // xWen 140 // | fWen xsTrap 141 // | | vWen | noSpec 142 // | | | mWen | | blockBack 143 // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 144 List (src1, src2, src3, fu, fuOp, N, N, Y, N, N, N, N, N, Y, SelImm.X) 145 } 146} 147 148object VecDecoder extends DecodeConstants { 149 private def F = false 150 private def T = true 151 152 val opivv: Array[(BitPat, VecType)] = Array( 153 VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 154 VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 155 156 VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 157 VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 158 VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 159 VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 160 161 VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 162 VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 163 VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 164 165 VRGATHER_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 166 VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 167 168 VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 169 VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 170 VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 171 172 VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 173 VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 174 VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 175 176 VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 177 178 VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 179 VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 180 VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 181 VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 182 VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 183 VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 184 185 VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 186 VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 187 VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 188 VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 189 VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 190 191 VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 192 VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 193 VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 194 VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 195 196 VSMUL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 197 198 VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 199 VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 200 201 VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 202 VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 203 204 VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 205 VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 206 ) 207 208 val opivx: Array[(BitPat, VecType)] = Array( 209 VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 210 VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 211 VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 212 213 VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 214 VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 215 VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 216 VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 217 218 VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 219 VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 220 VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 221 222 VRGATHER_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 223 224 VSLIDEUP_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 225 VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 226 227 VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 228 VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 229 VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 230 VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 231 VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 232 233 VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 234 235 VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 236 VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 237 VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 238 VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 239 VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 240 VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 241 VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 242 VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 243 244 VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 245 VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 246 VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 247 VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 248 VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 249 250 VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 251 VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 252 VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 253 VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 254 255 256 VSMUL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 257 258 VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 259 VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 260 261 VNCLIPU_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 262 VNCLIP_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 263 ) 264 265 val opivi: Array[(BitPat, VecType)] = Array( 266 VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 267 VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 268 269 VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 270 VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 271 VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 272 273 VRGATHER_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 274 275 VSLIDEUP_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 276 VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 277 278 VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 279 VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 280 281 VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 282 283 VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 284 VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 285 VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 286 VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 287 VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 288 VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 289 290 VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 291 VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 292 VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 293 VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 294 VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 295 296 VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 297 VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 298 299 VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 300 VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 301 302 VNCLIPU_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 303 VNCLIP_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 304 305 VMV1R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 306 VMV2R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 307 VMV4R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 308 VMV8R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 309 ) 310 311 val opmvv: Array[(BitPat, VecType)] = Array( 312 VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 313 VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 314 VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 315 VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 316 VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 317 VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 318 VDIV_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 319 VDIVU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 320 VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 321 VID_V -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 322 VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 323 VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 324 VMADD_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 325 VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 326 VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 327 VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 328 VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 329 VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 330 VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 331 VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 332 VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 333 VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 334 VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 335 VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 336 VMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 337 VMULH_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 338 VMULHSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 339 VMULHU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 340 VMV_X_S -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 341 VNMSAC_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 342 VNMSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 343 VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 344 VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 345 VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 346 VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 347 VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 348 VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 349 VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 350 VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 351 VREM_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 352 VREMU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 353 VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 354 VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 355 VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 356 VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 357 VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 358 VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 359 VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 360 VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 361 VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 362 VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 363 VWMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 364 VWMACCSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 365 VWMACCU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 366 VWMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 367 VWMULSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 368 VWMULU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 369 VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 370 VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 371 VWSUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 372 VWSUBU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F) 373 ) 374 375 val opmvx: Array[(BitPat, VecType)] = Array( 376 VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 377 VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 378 VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 379 VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 380 VDIV_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 381 VDIVU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 382 VMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 383 VMADD_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 384 VMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 385 VMULH_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 386 VMULHSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 387 VMULHU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 388 VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 389 VNMSAC_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 390 VNMSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 391 VREM_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 392 VREMU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 393 VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 394 VSLIDE1UP_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 395 VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 396 VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 397 VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 398 VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 399 VWMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 400 VWMACCSU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 401 VWMACCU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 402 VWMACCUS_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 403 VWMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 404 VWMULSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 405 VWMULU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 406 VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 407 VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 408 VWSUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 409 VWSUBU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F) 410 ) 411 412 val opfvv: Array[(BitPat, VecType)] = Array( 413 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 414 VFADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 415 VFSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 416 417 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 418 VFWADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 419 VFWSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 420 VFWADD_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 421 VFWSUB_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 422 423 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 424 VFMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 425 VFDIV_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 426 427 // 13.5. Vector Widening Floating-Point Multiply 428 VFWMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 429 430 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 431 VFMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 432 VFNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 433 VFMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 434 VFNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 435 VFMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 436 VFNMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 437 VFMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 438 VFNMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 439 440 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 441 VFWMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 442 VFWNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 443 VFWMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 444 VFWNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 445 446 // 13.8. Vector Floating-Point Square-Root Instruction 447 VFSQRT_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 448 449 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 450 VFRSQRT7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 451 452 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction 453 VFREC7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 454 455 // 13.11. Vector Floating-Point MIN/MAX Instructions 456 VFMIN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 457 VFMAX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 458 459 // 13.12. Vector Floating-Point Sign-Injection Instructions 460 VFSGNJ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 461 VFSGNJN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 462 VFSGNJX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 463 464 // 13.13. Vector Floating-Point Compare Instructions 465 VMFEQ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 466 VMFNE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 467 VMFLT_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 468 VMFLE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 469 470 // 13.14. Vector Floating-Point Classify Instruction 471 VFCLASS_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 472 473 // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 474 VFCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 475 VFCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 476 VFCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 477 VFCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 478 VFCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 479 VFCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 480 481 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions 482 VFWCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 483 VFWCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 484 VFWCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 485 VFWCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 486 VFWCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 487 VFWCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 488 VFWCVT_F_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 489 490 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 491 VFNCVT_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 492 VFNCVT_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 493 VFNCVT_RTZ_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 494 VFNCVT_RTZ_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 495 VFNCVT_F_XU_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 496 VFNCVT_F_X_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 497 VFNCVT_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 498 VFNCVT_ROD_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 499 500 // 14.3. Vector Single-Width Floating-Point Reduction Instructions 501 VFREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 502 VFREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 503 VFREDMAX_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 504 VFREDMIN_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 505 506 // 14.4. Vector Widening Floating-Point Reduction Instructions 507 VFWREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 508 VFWREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 509 510 // 16.2. Floating-Point Scalar Move Instructions 511 VFMV_F_S -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// f[rd] = vs2[0] (rs1=0) 512 ) 513 514 val opfvf: Array[(BitPat, VecType)] = Array( 515 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 516 VFADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 517 VFSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 518 VFRSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 519 520 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 521 VFWADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 522 VFWSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 523 VFWADD_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 524 VFWSUB_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 525 526 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 527 VFMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 528 VFDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 529 VFRDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 530 531 // 13.5. Vector Widening Floating-Point Multiply 532 VFWMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 533 534 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 535 VFMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 536 VFNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 537 VFMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 538 VFNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 539 VFMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 540 VFNMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 541 VFMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 542 VFNMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 543 544 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 545 VFWMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 546 VFWNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 547 VFWMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 548 VFWNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 549 550 // 13.11. Vector Floating-Point MIN/MAX Instructions 551 VFMIN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 552 VFMAX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 553 554 // 13.12. Vector Floating-Point Sign-Injection Instructions 555 VFSGNJ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 556 VFSGNJN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 557 VFSGNJX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 558 559 // 13.13. Vector Floating-Point Compare Instructions 560 VMFEQ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 561 VMFNE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 562 VMFLT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 563 VMFLE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 564 VMFGT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 565 VMFGE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 566 567 // 13.15. Vector Floating-Point Merge Instruction 568 VFMERGE_VFM -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 569 570 // 13.16. Vector Floating-Point Move Instruction 571 VFMV_V_F -> OPFVF(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// src2=SrcType.X 572 573 // 16.2. Floating-Point Scalar Move Instructions 574 VFMV_S_F -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vs2=0 575 576 // 16.3.3. Vector Slide1up 577 // vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] 578 VFSLIDE1UP_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[0]=f[rs1], vd[i+1] = vs2[i] 579 580 // 16.3.4. Vector Slide1down Instruction 581 // vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] 582 VFSLIDE1DOWN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1] 583 ) 584 585 val vset: Array[(BitPat, VecType)] = Array( 586 VSETVLI -> VSET(F, T, ALUOpType.vsetvli, F, SelImm.IMM_VSETVLI), 587 VSETIVLI -> VSET(T, T, ALUOpType.vsetivli, F, SelImm.IMM_VSETIVLI), 588 VSETVL -> VSET(F, F, ALUOpType.vsetvl, T, SelImm.X), // flush pipe 589 ) 590 591 val vls: Array[(BitPat, VecType)] = Array( 592 // 7.4. Vector Unit-Stride Instructions 593 VLE8_V -> VLD(SrcType.X, VlduType.dummy), 594 VLE16_V -> VLD(SrcType.X, VlduType.dummy), 595 VLE32_V -> VLD(SrcType.X, VlduType.dummy), 596 VLE64_V -> VLD(SrcType.X, VlduType.dummy), 597 VSE8_V -> VST(SrcType.X, VstuType.dummy), 598 VSE16_V -> VST(SrcType.X, VstuType.dummy), 599 VSE32_V -> VST(SrcType.X, VstuType.dummy), 600 VSE64_V -> VST(SrcType.X, VstuType.dummy), 601 VLM_V -> VLD(SrcType.X, VlduType.dummy, mask = T), 602 VSM_V -> VST(SrcType.X, VstuType.dummy, mask = T), 603 // 7.5. Vector Strided Instructions 604 VLSE8_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 605 VLSE16_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 606 VLSE32_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 607 VLSE64_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 608 VSSE8_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 609 VSSE16_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 610 VSSE32_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 611 VSSE64_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 612 // 7.6. Vector Indexed Instructions 613 VLUXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 614 VLUXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 615 VLUXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 616 VLUXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 617 VLOXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 618 VLOXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 619 VLOXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 620 VLOXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 621 VSUXEI8_V -> VLD(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 622 VSUXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 623 VSUXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 624 VSUXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 625 VSOXEI8_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 626 VSOXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 627 VSOXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 628 VSOXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 629 // 7.7. Unit-stride Fault-Only-First Loads 630 VLE8FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 631 VLE16FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 632 VLE32FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 633 VLE64FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 634 // 7.8. Vector Load/Store Segment Instructions 635 // 7.8.1. Vector Unit-Stride Segment Loads and Stores 636 // TODO 637 // 7.8.2. Vector Strided Segment Loads and Stores 638 // TODO 639 // 7.8.3. Vector Indexed Segment Loads and Stores 640 // TODO 641 // 7.9. Vector Load/Store Whole Register Instructions 642 VL1RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 643 VL1RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 644 VL1RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 645 VL1RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 646 VL2RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 647 VL2RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 648 VL2RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 649 VL2RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 650 VL4RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 651 VL4RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 652 VL4RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 653 VL4RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 654 VL8RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 655 VL8RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 656 VL8RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 657 VL8RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 658 VS1R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 659 VS2R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 660 VS4R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 661 VS8R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 662 ) 663 664 val opivvTable : Array[(BitPat, List[BitPat])] = opivv.map(x => (x._1, x._2.generate())) 665 val opivxTable : Array[(BitPat, List[BitPat])] = opivx.map(x => (x._1, x._2.generate())) 666 val opiviTable : Array[(BitPat, List[BitPat])] = opivi.map(x => (x._1, x._2.generate())) 667 val opmvvTable : Array[(BitPat, List[BitPat])] = opmvv.map(x => (x._1, x._2.generate())) 668 val opmvxTable : Array[(BitPat, List[BitPat])] = opmvx.map(x => (x._1, x._2.generate())) 669 val opfvvTable : Array[(BitPat, List[BitPat])] = opfvv.map(x => (x._1, x._2.generate())) 670 val opfvfTable : Array[(BitPat, List[BitPat])] = opfvv.map(x => (x._1, x._2.generate())) 671 val vsetTable : Array[(BitPat, List[BitPat])] = vset.map(x => (x._1, x._2.generate())) 672 val vlsTable : Array[(BitPat, List[BitPat])] = vls.map(x => (x._1, x._2.generate())) 673 674 val table: Array[(BitPat, List[BitPat])] = opivvTable ++ opivxTable ++ opiviTable ++ 675 opmvvTable ++ opmvxTable ++ 676 opfvvTable ++ opfvfTable ++ 677 vsetTable ++ vlsTable 678} 679