xref: /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala (revision 7f2b7720ff1889edcfc44902e64e1a082b775d9b) 
1package xiangshan.backend.decode
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.util.uintToBitPat
7import utils._
8import xiangshan.ExceptionNO.illegalInstr
9import xiangshan._
10import freechips.rocketchip.rocket.Instructions._
11
12abstract class VecType {
13  def X = BitPat("b?")
14  def N = BitPat("b0")
15  def Y = BitPat("b1")
16  def generate() : List[BitPat]
17  def asOldDecodeOutput(): List[BitPat] = {
18    val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate()
19    List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm)
20  }
21}
22
23case class OPIVV(fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean) extends VecType {
24  def generate() : List[BitPat] = {
25    List (SrcType.vp, SrcType.vp, SrcType.X, fu, fuOp, N, N, vWen.B, mWen.B, N, N, N, N, SelImm.X)
26  }
27}
28
29case class OPIVX() extends VecType {
30  def generate() : List[BitPat] = { null }
31}
32
33case class OPIVI() extends VecType {
34  def generate() : List[BitPat] = { null }
35}
36
37case class OPMVV(fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) extends VecType {
38  def generate() : List[BitPat] = {
39    List (SrcType.vp, SrcType.vp, SrcType.X, fu, fuOp, xWen.B, N, vWen.B, mWen.B, N, N, N, N, SelImm.X)
40  }
41}
42
43case class OPMVX() extends VecType {
44  def generate() : List[BitPat] = { null }
45}
46
47case class OPFVV() extends VecType {
48  def generate() : List[BitPat] = { null }
49}
50
51case class OPFVF(fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType {
52  def generate() : List[BitPat] = {
53    List (SrcType.vp, SrcType.fp, SrcType.X, fu, fuOp, N, fWen.B, vWen.B, mWen.B, N, N, N, N, SelImm.X)
54  }
55}
56
57case class VSET() extends VecType {
58  def generate() : List[BitPat] = { null }
59}
60
61case class VLS() extends VecType {
62  def generate() : List[BitPat] = { null }
63}
64
65object VecDecoder extends DecodeConstants {
66  private def F = false
67  private def T = true
68
69  val opivvTable: Array[(BitPat, List[BitPat])] = Array(
70    VADD_VV   -> OPIVV(FuType.vipu, VipuType.dummy, T, F).generate(),
71
72    VMSEQ_VV  -> OPIVV(FuType.vipu, VipuType.dummy, F, T).generate(),
73  )
74
75  val opivxTable: Array[(BitPat, List[BitPat])] = Array()
76  val opiviTable: Array[(BitPat, List[BitPat])] = Array()
77
78  val opmvvTable: Array[(BitPat, List[BitPat])] = Array()
79  val opmvxTable: Array[(BitPat, List[BitPat])] = Array()
80
81  val opfvvTable: Array[(BitPat, List[BitPat])] = Array()
82
83  val opfvfTable: Array[(BitPat, List[BitPat])] = Array(
84    VFADD_VF  -> OPFVF(FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
85    VMFEQ_VF  -> OPFVF(FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
86  )
87
88  val vsetTable: Array[(BitPat, List[BitPat])] = Array()
89  val vlsTable: Array[(BitPat, List[BitPat])] = Array()
90
91  val table = opivvTable ++ opivxTable ++ opiviTable ++
92              opmvvTable ++ opmvxTable ++
93              opfvvTable ++ opfvfTable ++
94              vsetTable ++ vlsTable
95}
96