xref: /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala (revision 58c35d23a1fbddf24e21e0bc8caec56906ae8c3c) 
1package xiangshan.backend.decode
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.util.uintToBitPat
7import freechips.rocketchip.rocket.Instructions._
8import utils._
9import xiangshan.ExceptionNO.illegalInstr
10import xiangshan._
11import yunsuan.{VipuType, VfpuType}
12
13abstract class VecType {
14  def X = BitPat("b?")
15  def N = BitPat("b0")
16  def Y = BitPat("b1")
17  def generate() : List[BitPat]
18  def asOldDecodeOutput(): List[BitPat] = {
19    val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate()
20    List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm)
21  }
22}
23
24case class OPIVV(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType {
25  def generate() : List[BitPat] = {
26    List (SrcType.vp, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, SelImm.X)
27  }
28}
29
30case class OPIVX(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType {
31  def generate() : List[BitPat] = {
32    List (SrcType.xp, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, SelImm.X)
33  }
34}
35
36case class OPIVI(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean, selImm: BitPat) extends VecType {
37  def generate() : List[BitPat] = {
38    List (SrcType.imm, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, selImm)
39  }
40}
41
42case class OPMVV(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) extends VecType {
43  private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X
44  def generate() : List[BitPat] = {
45    List (SrcType.vp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, N, N, N, N, SelImm.X)
46  }
47}
48
49case class OPMVX(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) extends VecType {
50  private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X
51  def generate() : List[BitPat] = {
52    List (SrcType.xp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, N, N, N, N, SelImm.X)
53  }
54}
55
56case class OPFVV(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat,  fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType {
57  def generate() : List[BitPat] = {
58    List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, N, N, N, N, SelImm.X)
59  }
60}
61
62case class OPFVF(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType {
63  def generate() : List[BitPat] = {
64    List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, N, N, N, N, SelImm.X)
65  }
66}
67
68case class VSET() extends VecType {
69  def generate() : List[BitPat] = { null }
70}
71
72case class VLS() extends VecType {
73  def generate() : List[BitPat] = { null }
74}
75
76object VecDecoder extends DecodeConstants {
77  private def F = false
78  private def T = true
79
80  val opivvTable: Array[(BitPat, List[BitPat])] = Array(
81    VADD_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
82    VSUB_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
83
84    VMINU_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
85    VMIN_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
86    VMAXU_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
87    VMAX_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
88
89    VAND_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
90    VOR_VV          -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
91    VXOR_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
92
93    VRGATHER_VV     -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
94    VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
95
96    VADC_VVM        -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
97    VMADC_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
98    VMADC_VVM       -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(),
99
100    VSBC_VVM        -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
101    VMSBC_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
102    VMSBC_VVM       -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(),
103
104    VMERGE_VVM      -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
105
106    VMSEQ_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
107    VMSNE_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
108    VMSLTU_VV       -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
109    VMSLT_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
110    VMSLEU_VV       -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
111    VMSLE_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
112
113    VSLL_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
114    VSRL_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
115    VSRA_VV         -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
116    VNSRL_WV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
117    VNSRA_WV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
118
119    VSADDU_VV       -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
120    VSADD_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
121    VSSUBU_VV       -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
122    VSSUB_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
123
124    VSMUL_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
125
126    VSSRL_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
127    VSSRA_VV        -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
128
129    VNCLIPU_WV      -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
130    VNCLIP_WV       -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
131
132    VWREDSUMU_VS    -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
133    VWREDSUM_VS     -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
134  )
135
136  val opivxTable: Array[(BitPat, List[BitPat])] = Array(
137    VADD_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
138    VSUB_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
139    VRSUB_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
140
141    VMINU_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
142    VMIN_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
143    VMAXU_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
144    VMAX_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
145
146    VAND_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
147    VOR_VX        -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
148    VXOR_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
149
150    VRGATHER_VX   -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
151
152    VSLIDEUP_VX   -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
153    VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
154
155    VADC_VXM      -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
156    VMADC_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
157    VSBC_VXM      -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
158    VMSBC_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
159    VMSBC_VXM     -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(),
160
161    VMERGE_VXM    -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(),
162
163    VMSEQ_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
164    VMSNE_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
165    VMSLTU_VX     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
166    VMSLT_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
167    VMSLEU_VX     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
168    VMSLE_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
169    VMSGTU_VX     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
170    VMSGT_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(),
171
172    VSLL_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
173    VSRL_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
174    VSRA_VX       -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
175    VNSRL_WX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
176    VNSRA_WX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
177
178    VSADDU_VX     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
179    VSADD_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
180    VSSUBU_VX     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
181    VSSUB_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
182
183
184    VSMUL_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
185
186    VSSRL_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
187    VSSRA_VX      -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(),
188
189    VNCLIPU_WV    -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
190    VNCLIP_WV     -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(),
191  )
192
193  val opiviTable: Array[(BitPat, List[BitPat])] = Array(
194    VADD_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
195    VRSUB_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
196
197    VAND_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
198    VOR_VI        -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
199    VXOR_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
200
201    VRGATHER_VI   -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
202
203    VSLIDEUP_VI   -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
204    VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
205
206    VADC_VIM      -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
207    VMADC_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
208
209    VMERGE_VIM    -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
210
211    VMSEQ_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
212    VMSNE_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
213    VMSLEU_VI     -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
214    VMSLE_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
215    VMSGTU_VI     -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
216    VMSGT_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(),
217
218    VSLL_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
219    VSRL_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
220    VSRA_VI       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
221    VNSRL_WI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
222    VNSRA_WI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
223
224    VSADDU_VI     -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS).generate(),
225    VSADD_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS).generate(),
226
227    VSSRL_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
228    VSSRA_VI      -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(),
229
230    VNCLIPU_WV    -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU).generate(),
231    VNCLIP_WV     -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU).generate(),
232
233    VMV1R_V       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
234    VMV2R_V       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
235    VMV4R_V       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
236    VMV8R_V       -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(),
237  )
238
239  val opmvv: Array[(BitPat, OPMVV)] = Array(
240    VAADD_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
241    VAADDU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
242    VASUB_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
243    VASUBU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
244    VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
245    VCPOP_M      -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T),
246    VDIV_VV      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
247    VDIVU_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
248    VFIRST_M     -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T),
249    VID_V        -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
250    VIOTA_M      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
251    VMACC_VV     -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T),
252    VMADD_VV     -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T),
253    VMAND_MM     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
254    VMANDN_MM    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
255    VMNAND_MM    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
256    VMNOR_MM     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
257    VMOR_MM      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
258    VMORN_MM     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
259    VMXNOR_MM    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
260    VMXOR_MM     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
261    VMSBF_M      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
262    VMSIF_M      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
263    VMSOF_M      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
264    VMUL_VV      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
265    VMULH_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
266    VMULHSU_VV   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
267    VMULHU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
268    VMV_X_S      -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T),
269    VNMSAC_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
270    VNMSUB_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
271    VREDAND_VS   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
272    VREDMAX_VS   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
273    VREDMAXU_VS  -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
274    VREDMIN_VS   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
275    VREDMINU_VS  -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
276    VREDOR_VS    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
277    VREDSUM_VS   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
278    VREDXOR_VS   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
279    VREM_VV      -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
280    VREMU_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
281    VSEXT_VF2    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
282    VSEXT_VF4    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
283    VSEXT_VF8    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
284    VZEXT_VF2    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
285    VZEXT_VF4    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
286    VZEXT_VF8    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
287    VWADD_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
288    VWADD_WV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
289    VWADDU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
290    VWADDU_WV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
291    VWMACC_VV    -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T),
292    VWMACCSU_VV  -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T),
293    VWMACCU_VV   -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T),
294    VWMUL_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
295    VWMULSU_VV   -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
296    VWMULU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
297    VWSUB_VV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
298    VWSUB_WV     -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
299    VWSUBU_VV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T),
300    VWSUBU_WV    -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T)
301  )
302  val opmvx: Array[(BitPat, OPMVX)] = Array(
303    VAADD_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
304    VAADDU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
305    VASUB_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
306    VASUBU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
307    VDIV_VX        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
308    VDIVU_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
309    VMACC_VX       -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
310    VMADD_VX       -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
311    VMUL_VX        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
312    VMULH_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
313    VMULHSU_VX     -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
314    VMULHU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
315    VMV_S_X        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
316    VNMSAC_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
317    VNMSUB_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
318    VREM_VX        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
319    VREMU_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
320    VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
321    VSLIDE1UP_VX   -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
322    VWADD_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
323    VWADD_WX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
324    VWADDU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
325    VWADDU_WX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
326    VWMACC_VX      -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
327    VWMACCSU_VX    -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
328    VWMACCU_VX     -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
329    VWMACCUS_VX    -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T),
330    VWMUL_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
331    VWMULSU_VX     -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
332    VWMULU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
333    VWSUB_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
334    VWSUB_WX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
335    VWSUBU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T),
336    VWSUBU_WX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T)
337  )
338  val opmvvTable: Array[(BitPat, List[BitPat])] = opmvv.map(x => (x._1, x._2.generate()))
339  val opmvxTable: Array[(BitPat, List[BitPat])] = opmvx.map(x => (x._1, x._2.generate()))
340
341
342  val opfvvTable: Array[(BitPat, List[BitPat])] = Array(
343                       // OPFVV(fu: BitPat, fuOp: BitPat,  fWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any)
344// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
345VFADD_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
346VFSUB_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
347
348// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
349VFWADD_VV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
350VFWSUB_VV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
351VFWADD_WV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
352VFWSUB_WV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
353
354// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
355VFMUL_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
356VFDIV_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
357
358// 13.5. Vector Widening Floating-Point Multiply
359VFWMUL_VV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
360
361// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
362VFMACC_VV          -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
363VFNMACC_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
364VFMSAC_VV          -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
365VFNMSAC_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
366VFMADD_VV          -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
367VFNMADD_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
368VFMSUB_VV          -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
369VFNMSUB_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
370
371// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
372VFWMACC_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
373VFWNMACC_VV        -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
374VFWMSAC_VV         -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
375VFWNMSAC_VV        -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
376
377// 13.8. Vector Floating-Point Square-Root Instruction
378VFSQRT_V           -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
379
380// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
381VFRSQRT7_V         -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
382
383// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
384VFREC7_V           -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
385
386// 13.11. Vector Floating-Point MIN/MAX Instructions
387VFMIN_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
388VFMAX_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
389
390// 13.12. Vector Floating-Point Sign-Injection Instructions
391VFSGNJ_VV          -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
392VFSGNJN_VV         -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
393VFSGNJX_VV         -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
394
395// 13.13. Vector Floating-Point Compare Instructions
396VMFEQ_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
397VMFNE_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
398VMFLT_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
399VMFLE_VV           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
400
401// 13.14. Vector Floating-Point Classify Instruction
402VFCLASS_V          -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
403
404// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
405VFCVT_XU_F_V       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
406VFCVT_X_F_V        -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
407VFCVT_RTZ_XU_F_V   -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
408VFCVT_RTZ_X_F_V    -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
409VFCVT_F_XU_V       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
410VFCVT_F_X_V        -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
411
412// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
413VFWCVT_XU_F_V      -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
414VFWCVT_X_F_V       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
415VFWCVT_RTZ_XU_F_V  -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
416VFWCVT_RTZ_X_F_V   -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
417VFWCVT_F_XU_V      -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
418VFWCVT_F_X_V       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
419VFWCVT_F_F_V       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
420
421// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
422VFNCVT_XU_F_W      -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
423VFNCVT_X_F_W       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
424VFNCVT_RTZ_XU_F_W  -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
425VFNCVT_RTZ_X_F_W   -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
426VFNCVT_F_XU_W      -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
427VFNCVT_F_X_W       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
428VFNCVT_F_F_W       -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
429VFNCVT_ROD_F_F_W   -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
430
431// 14.3. Vector Single-Width Floating-Point Reduction Instructions
432VFREDOSUM_VS       -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
433VFREDUSUM_VS       -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
434VFREDMAX_VS        -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
435VFREDMIN_VS        -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
436
437// 14.4. Vector Widening Floating-Point Reduction Instructions
438VFWREDOSUM_VS      -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
439VFWREDUSUM_VS      -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
440
441// 16.2. Floating-Point Scalar Move Instructions
442VFMV_F_S           -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// f[rd] = vs2[0] (rs1=0)
443
444
445
446  )
447
448  val opfvfTable: Array[(BitPat, List[BitPat])] = Array(
449// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
450VFADD_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
451VFSUB_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
452VFRSUB_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
453
454// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
455VFWADD_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
456VFWSUB_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
457VFWADD_WF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
458VFWSUB_WF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
459
460// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
461VFMUL_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
462VFDIV_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
463VFRDIV_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
464
465// 13.5. Vector Widening Floating-Point Multiply
466VFWMUL_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
467
468// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
469VFMACC_VF          -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
470VFNMACC_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
471VFMSAC_VF          -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
472VFNMSAC_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
473VFMADD_VF          -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
474VFNMADD_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
475VFMSUB_VF          -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
476VFNMSUB_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
477
478// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
479VFWMACC_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
480VFWNMACC_VF        -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
481VFWMSAC_VF         -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
482VFWNMSAC_VF        -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
483
484// 13.11. Vector Floating-Point MIN/MAX Instructions
485VFMIN_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
486VFMAX_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
487
488// 13.12. Vector Floating-Point Sign-Injection Instructions
489VFSGNJ_VF          -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
490VFSGNJN_VF         -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
491VFSGNJX_VF         -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
492
493// 13.13. Vector Floating-Point Compare Instructions
494VMFEQ_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
495VMFNE_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
496VMFLT_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
497VMFLE_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
498VMFGT_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
499VMFGE_VF           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(),
500
501// 13.15. Vector Floating-Point Merge Instruction
502VFMERGE_VFM        -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),
503
504// 13.16. Vector Floating-Point Move Instruction
505VFMV_V_F           -> OPFVF(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// src2=SrcType.X
506
507// 16.2. Floating-Point Scalar Move Instructions
508VFMV_S_F           -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vs2=0
509
510// 16.3.3. Vector Slide1up
511// vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i]
512VFSLIDE1UP_VF      -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vd[0]=f[rs1], vd[i+1] = vs2[i]
513
514// 16.3.4. Vector Slide1down Instruction
515// vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
516VFSLIDE1DOWN_VF    -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
517
518  )
519
520  val vsetTable: Array[(BitPat, List[BitPat])] = Array()
521  val vlsTable: Array[(BitPat, List[BitPat])] = Array()
522
523  val table = opivvTable ++ opivxTable ++ opiviTable ++
524              opmvvTable ++ opmvxTable ++
525              opfvvTable ++ opfvfTable ++
526              vsetTable ++ vlsTable
527}
528