17f2b7720SXuan Hupackage xiangshan.backend.decode 27f2b7720SXuan Hu 37f2b7720SXuan Huimport chipsalliance.rocketchip.config.Parameters 47f2b7720SXuan Huimport chisel3._ 5912e2179SXuan Huimport chisel3.util.BitPat.bitPatToUInt 67f2b7720SXuan Huimport chisel3.util._ 77f2b7720SXuan Huimport freechips.rocketchip.util.uintToBitPat 83a2e64c4SZhangZifeiimport freechips.rocketchip.rocket.Instructions._ 97f2b7720SXuan Huimport utils._ 107f2b7720SXuan Huimport xiangshan.ExceptionNO.illegalInstr 117f2b7720SXuan Huimport xiangshan._ 12912e2179SXuan Huimport yunsuan.{VfpuType, VipuType} 137f2b7720SXuan Hu 14*b65b9ebaSXuan Huabstract class VecDecode extends XSDecodeBase { 157f2b7720SXuan Hu def generate() : List[BitPat] 167f2b7720SXuan Hu def asOldDecodeOutput(): List[BitPat] = { 17912e2179SXuan Hu val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 187f2b7720SXuan Hu List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm) 197f2b7720SXuan Hu } 20912e2179SXuan Hu def asFirstStageDecodeOutput(): List[BitPat] = { 21912e2179SXuan Hu val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 22912e2179SXuan Hu List (src1, src2, src3, fu, fuOp, xWen, fWen, bitPatToUInt(vWen) | bitPatToUInt(mWen), xsTrap, noSpec, blockBack, flushPipe, selImm) 23912e2179SXuan Hu } 247f2b7720SXuan Hu} 257f2b7720SXuan Hu 26*b65b9ebaSXuan Hucase class OPIVV(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends XSDecodeBase { 277f2b7720SXuan Hu def generate() : List[BitPat] = { 28*b65b9ebaSXuan Hu XSDecode(SrcType.vp, SrcType.vp, src3, fu, fuOp, SelImm.X, 29*b65b9ebaSXuan Hu xWen = F, fWen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 307f2b7720SXuan Hu } 317f2b7720SXuan Hu} 327f2b7720SXuan Hu 33*b65b9ebaSXuan Hucase class OPIVX(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends XSDecodeBase { 3458c35d23Shuxuan0307 def generate() : List[BitPat] = { 35*b65b9ebaSXuan Hu XSDecode(SrcType.xp, SrcType.vp, src3, fu, fuOp, SelImm.X, 36*b65b9ebaSXuan Hu xWen = F, fWen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 3758c35d23Shuxuan0307 } 387f2b7720SXuan Hu} 397f2b7720SXuan Hu 40*b65b9ebaSXuan Hucase class OPIVI(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean, selImm: BitPat) extends XSDecodeBase { 4158c35d23Shuxuan0307 def generate() : List[BitPat] = { 42*b65b9ebaSXuan Hu XSDecode(SrcType.imm, SrcType.vp, src3, fu, fuOp, selImm, 43*b65b9ebaSXuan Hu xWen = F, fWen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 4458c35d23Shuxuan0307 } 457f2b7720SXuan Hu} 467f2b7720SXuan Hu 47*b65b9ebaSXuan Hucase class OPMVV(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends XSDecodeBase { 48c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 497f2b7720SXuan Hu def generate() : List[BitPat] = { 50*b65b9ebaSXuan Hu XSDecode(SrcType.vp, SrcType.vp, src3, fu, fuOp, SelImm.X, xWen, F, vWen, mWen, F, F, F, F).generate() 517f2b7720SXuan Hu } 527f2b7720SXuan Hu} 537f2b7720SXuan Hu 54*b65b9ebaSXuan Hucase class OPMVX(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends XSDecodeBase { 55c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 56c6661c33SHaojin Tang def generate() : List[BitPat] = { 57*b65b9ebaSXuan Hu XSDecode(SrcType.xp, SrcType.vp, src3, fu, fuOp, SelImm.X, 58*b65b9ebaSXuan Hu xWen = xWen, fWen = F, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 59c6661c33SHaojin Tang } 607f2b7720SXuan Hu} 617f2b7720SXuan Hu 62*b65b9ebaSXuan Hucase class OPFVV(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends XSDecodeBase { 63b448988dSczw def generate() : List[BitPat] = { 64*b65b9ebaSXuan Hu XSDecode(src1, SrcType.vp, src3, fu, fuOp, SelImm.X, 65*b65b9ebaSXuan Hu xWen = F, fWen = fWen, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 66b448988dSczw } 677f2b7720SXuan Hu} 687f2b7720SXuan Hu 69*b65b9ebaSXuan Hucase class OPFVF(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends XSDecodeBase { 707f2b7720SXuan Hu def generate() : List[BitPat] = { 71*b65b9ebaSXuan Hu XSDecode(src1, SrcType.vp, src3, fu, fuOp, SelImm.X, 72*b65b9ebaSXuan Hu xWen = F, fWen = fWen, vWen = vWen, mWen = mWen, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 737f2b7720SXuan Hu } 747f2b7720SXuan Hu} 757f2b7720SXuan Hu 76*b65b9ebaSXuan Hucase class VSET(vli: Boolean, vtypei: Boolean, fuOp: BitPat, flushPipe: Boolean, selImm: BitPat) extends XSDecodeBase { 77912e2179SXuan Hu def generate() : List[BitPat] = { 78912e2179SXuan Hu val src1 = if (vli) SrcType.imm else SrcType.xp 79912e2179SXuan Hu val src2 = if (vtypei) SrcType.imm else SrcType.xp 80*b65b9ebaSXuan Hu XSDecode(src1, src2, SrcType.X, FuType.alu, fuOp, selImm, 81*b65b9ebaSXuan Hu xWen = T, fWen = F, vWen = F, mWen = F, xsTrap = F, noSpec = F, blockBack = F, flushPipe = flushPipe).generate() 82912e2179SXuan Hu } 837f2b7720SXuan Hu} 847f2b7720SXuan Hu 85912e2179SXuan Hucase class VLD(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, ff: Boolean = false, 86*b65b9ebaSXuan Hu mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends XSDecodeBase { 87912e2179SXuan Hu def generate() : List[BitPat] = { 88912e2179SXuan Hu val fu = FuType.vldu 89912e2179SXuan Hu val src1 = SrcType.xp 90912e2179SXuan Hu val src3 = SrcType.X 91*b65b9ebaSXuan Hu XSDecode(src1, src2, src3, fu, fuOp, SelImm.X, 92*b65b9ebaSXuan Hu xWen = F, fWen = F, vWen = T, mWen = F, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 93912e2179SXuan Hu } 94912e2179SXuan Hu} 95912e2179SXuan Hu 96912e2179SXuan Hucase class VST(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, 97*b65b9ebaSXuan Hu mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends XSDecodeBase { 98912e2179SXuan Hu def generate() : List[BitPat] = { 99912e2179SXuan Hu val fu = FuType.vstu 100912e2179SXuan Hu val src1 = SrcType.xp 101912e2179SXuan Hu val src3 = SrcType.vp 102*b65b9ebaSXuan Hu XSDecode(src1, src2, src3, fu, fuOp, SelImm.X, 103*b65b9ebaSXuan Hu xWen = F, fWen = F, vWen = F, mWen = F, xsTrap = F, noSpec = F, blockBack = F, flushPipe = F).generate() 104912e2179SXuan Hu } 1057f2b7720SXuan Hu} 1067f2b7720SXuan Hu 1077f2b7720SXuan Huobject VecDecoder extends DecodeConstants { 108*b65b9ebaSXuan Hu val opivv: Array[(BitPat, XSDecodeBase)] = Array( 109912e2179SXuan Hu VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 110912e2179SXuan Hu VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 1117f2b7720SXuan Hu 112912e2179SXuan Hu VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 113912e2179SXuan Hu VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 114912e2179SXuan Hu VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 115912e2179SXuan Hu VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 11658c35d23Shuxuan0307 117912e2179SXuan Hu VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 118912e2179SXuan Hu VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 119912e2179SXuan Hu VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 12058c35d23Shuxuan0307 121912e2179SXuan Hu VRGATHER_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 122912e2179SXuan Hu VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 12358c35d23Shuxuan0307 124912e2179SXuan Hu VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 125912e2179SXuan Hu VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 126912e2179SXuan Hu VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 12758c35d23Shuxuan0307 128912e2179SXuan Hu VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 129912e2179SXuan Hu VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 130912e2179SXuan Hu VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 13158c35d23Shuxuan0307 132912e2179SXuan Hu VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 13358c35d23Shuxuan0307 134912e2179SXuan Hu VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 135912e2179SXuan Hu VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 136912e2179SXuan Hu VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 137912e2179SXuan Hu VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 138912e2179SXuan Hu VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 139912e2179SXuan Hu VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 14058c35d23Shuxuan0307 141912e2179SXuan Hu VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 142912e2179SXuan Hu VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 143912e2179SXuan Hu VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 144912e2179SXuan Hu VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 145912e2179SXuan Hu VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 14658c35d23Shuxuan0307 147912e2179SXuan Hu VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 148912e2179SXuan Hu VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 149912e2179SXuan Hu VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 150912e2179SXuan Hu VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 15158c35d23Shuxuan0307 152912e2179SXuan Hu VSMUL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 15358c35d23Shuxuan0307 154912e2179SXuan Hu VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 155912e2179SXuan Hu VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 15658c35d23Shuxuan0307 157912e2179SXuan Hu VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 158912e2179SXuan Hu VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 15958c35d23Shuxuan0307 160912e2179SXuan Hu VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 161912e2179SXuan Hu VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 1627f2b7720SXuan Hu ) 1637f2b7720SXuan Hu 164*b65b9ebaSXuan Hu val opivx: Array[(BitPat, XSDecodeBase)] = Array( 165912e2179SXuan Hu VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 166912e2179SXuan Hu VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 167912e2179SXuan Hu VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 16858c35d23Shuxuan0307 169912e2179SXuan Hu VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 170912e2179SXuan Hu VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 171912e2179SXuan Hu VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 172912e2179SXuan Hu VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 17358c35d23Shuxuan0307 174912e2179SXuan Hu VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 175912e2179SXuan Hu VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 176912e2179SXuan Hu VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 17758c35d23Shuxuan0307 178912e2179SXuan Hu VRGATHER_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 17958c35d23Shuxuan0307 180912e2179SXuan Hu VSLIDEUP_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 181912e2179SXuan Hu VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 18258c35d23Shuxuan0307 183912e2179SXuan Hu VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 184912e2179SXuan Hu VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 185912e2179SXuan Hu VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 186912e2179SXuan Hu VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 187912e2179SXuan Hu VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 18858c35d23Shuxuan0307 189912e2179SXuan Hu VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 19058c35d23Shuxuan0307 191912e2179SXuan Hu VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 192912e2179SXuan Hu VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 193912e2179SXuan Hu VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 194912e2179SXuan Hu VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 195912e2179SXuan Hu VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 196912e2179SXuan Hu VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 197912e2179SXuan Hu VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 198912e2179SXuan Hu VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 19958c35d23Shuxuan0307 200912e2179SXuan Hu VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 201912e2179SXuan Hu VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 202912e2179SXuan Hu VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 203912e2179SXuan Hu VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 204912e2179SXuan Hu VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 20558c35d23Shuxuan0307 206912e2179SXuan Hu VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 207912e2179SXuan Hu VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 208912e2179SXuan Hu VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 209912e2179SXuan Hu VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 21058c35d23Shuxuan0307 21158c35d23Shuxuan0307 212912e2179SXuan Hu VSMUL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 21358c35d23Shuxuan0307 214912e2179SXuan Hu VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 215912e2179SXuan Hu VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 21658c35d23Shuxuan0307 217*b65b9ebaSXuan Hu VNCLIPU_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 218*b65b9ebaSXuan Hu VNCLIP_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 21958c35d23Shuxuan0307 ) 22058c35d23Shuxuan0307 221*b65b9ebaSXuan Hu val opivi: Array[(BitPat, XSDecodeBase)] = Array( 222912e2179SXuan Hu VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 223912e2179SXuan Hu VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 22458c35d23Shuxuan0307 225912e2179SXuan Hu VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 226912e2179SXuan Hu VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 227912e2179SXuan Hu VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 22858c35d23Shuxuan0307 229912e2179SXuan Hu VRGATHER_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 23058c35d23Shuxuan0307 231912e2179SXuan Hu VSLIDEUP_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 232912e2179SXuan Hu VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 23358c35d23Shuxuan0307 234912e2179SXuan Hu VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 235912e2179SXuan Hu VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 23658c35d23Shuxuan0307 237912e2179SXuan Hu VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 23858c35d23Shuxuan0307 239912e2179SXuan Hu VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 240912e2179SXuan Hu VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 241912e2179SXuan Hu VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 242912e2179SXuan Hu VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 243912e2179SXuan Hu VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 244912e2179SXuan Hu VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 24558c35d23Shuxuan0307 246912e2179SXuan Hu VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 247912e2179SXuan Hu VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 248912e2179SXuan Hu VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 249912e2179SXuan Hu VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 250912e2179SXuan Hu VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 25158c35d23Shuxuan0307 252912e2179SXuan Hu VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 253912e2179SXuan Hu VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 25458c35d23Shuxuan0307 255912e2179SXuan Hu VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 256912e2179SXuan Hu VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 25758c35d23Shuxuan0307 258*b65b9ebaSXuan Hu VNCLIPU_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 259*b65b9ebaSXuan Hu VNCLIP_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 26058c35d23Shuxuan0307 261912e2179SXuan Hu VMV1R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 262912e2179SXuan Hu VMV2R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 263912e2179SXuan Hu VMV4R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 264912e2179SXuan Hu VMV8R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 26558c35d23Shuxuan0307 ) 2667f2b7720SXuan Hu 267*b65b9ebaSXuan Hu val opmvv: Array[(BitPat, XSDecodeBase)] = Array( 268912e2179SXuan Hu VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 269912e2179SXuan Hu VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 270912e2179SXuan Hu VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 271912e2179SXuan Hu VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 272912e2179SXuan Hu VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 273912e2179SXuan Hu VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 274912e2179SXuan Hu VDIV_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 275912e2179SXuan Hu VDIVU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 276912e2179SXuan Hu VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 277912e2179SXuan Hu VID_V -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 278912e2179SXuan Hu VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 279*b65b9ebaSXuan Hu 280*b65b9ebaSXuan Hu // VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 281*b65b9ebaSXuan Hu 282912e2179SXuan Hu VMADD_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 283912e2179SXuan Hu VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 284912e2179SXuan Hu VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 285912e2179SXuan Hu VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 286912e2179SXuan Hu VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 287912e2179SXuan Hu VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 288912e2179SXuan Hu VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 289912e2179SXuan Hu VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 290912e2179SXuan Hu VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 291912e2179SXuan Hu VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 292912e2179SXuan Hu VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 293912e2179SXuan Hu VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 294912e2179SXuan Hu VMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 295912e2179SXuan Hu VMULH_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 296912e2179SXuan Hu VMULHSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 297912e2179SXuan Hu VMULHU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 298*b65b9ebaSXuan Hu 299912e2179SXuan Hu VMV_X_S -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 300912e2179SXuan Hu VNMSAC_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 301912e2179SXuan Hu VNMSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 302912e2179SXuan Hu VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 303912e2179SXuan Hu VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 304912e2179SXuan Hu VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 305912e2179SXuan Hu VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 306912e2179SXuan Hu VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 307912e2179SXuan Hu VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 308912e2179SXuan Hu VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 309912e2179SXuan Hu VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 310912e2179SXuan Hu VREM_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 311912e2179SXuan Hu VREMU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 312912e2179SXuan Hu VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 313912e2179SXuan Hu VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 314912e2179SXuan Hu VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 315912e2179SXuan Hu VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 316912e2179SXuan Hu VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 317912e2179SXuan Hu VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 318912e2179SXuan Hu VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 319912e2179SXuan Hu VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 320912e2179SXuan Hu VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 321912e2179SXuan Hu VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 322912e2179SXuan Hu VWMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 323912e2179SXuan Hu VWMACCSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 324912e2179SXuan Hu VWMACCU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 325912e2179SXuan Hu VWMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 326912e2179SXuan Hu VWMULSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 327912e2179SXuan Hu VWMULU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 328912e2179SXuan Hu VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 329912e2179SXuan Hu VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 330912e2179SXuan Hu VWSUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 331*b65b9ebaSXuan Hu VWSUBU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 332c6661c33SHaojin Tang ) 333912e2179SXuan Hu 334*b65b9ebaSXuan Hu val opmvx: Array[(BitPat, XSDecodeBase)] = Array( 335912e2179SXuan Hu VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 336912e2179SXuan Hu VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 337912e2179SXuan Hu VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 338912e2179SXuan Hu VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 339912e2179SXuan Hu VDIV_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 340912e2179SXuan Hu VDIVU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 341912e2179SXuan Hu VMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 342912e2179SXuan Hu VMADD_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 343912e2179SXuan Hu VMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 344912e2179SXuan Hu VMULH_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 345912e2179SXuan Hu VMULHSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 346912e2179SXuan Hu VMULHU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 347912e2179SXuan Hu VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 348*b65b9ebaSXuan Hu 349912e2179SXuan Hu VNMSAC_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 350912e2179SXuan Hu VNMSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 351912e2179SXuan Hu VREM_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 352912e2179SXuan Hu VREMU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 353*b65b9ebaSXuan Hu 354912e2179SXuan Hu VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 355912e2179SXuan Hu VSLIDE1UP_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 356912e2179SXuan Hu VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 357912e2179SXuan Hu VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 358912e2179SXuan Hu VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 359912e2179SXuan Hu VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 360*b65b9ebaSXuan Hu 361*b65b9ebaSXuan Hu // OutOfMemoryError 362912e2179SXuan Hu VWMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 363912e2179SXuan Hu VWMACCSU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 364912e2179SXuan Hu VWMACCU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 365*b65b9ebaSXuan Hu 366912e2179SXuan Hu VWMACCUS_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 367912e2179SXuan Hu VWMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 368912e2179SXuan Hu VWMULSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 369*b65b9ebaSXuan Hu // Ok 370912e2179SXuan Hu VWMULU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 371912e2179SXuan Hu VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 372912e2179SXuan Hu VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 373912e2179SXuan Hu VWSUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 374*b65b9ebaSXuan Hu VWSUBU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 375c6661c33SHaojin Tang ) 3767f2b7720SXuan Hu 377*b65b9ebaSXuan Hu val opfvv: Array[(BitPat, XSDecodeBase)] = Array( 378b448988dSczw // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 379912e2179SXuan Hu VFADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 380912e2179SXuan Hu VFSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 381b448988dSczw 382b448988dSczw // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 383912e2179SXuan Hu VFWADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 384912e2179SXuan Hu VFWSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 385912e2179SXuan Hu VFWADD_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 386912e2179SXuan Hu VFWSUB_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 387b448988dSczw 388b448988dSczw // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 389912e2179SXuan Hu VFMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 390912e2179SXuan Hu VFDIV_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 391b448988dSczw 392b448988dSczw // 13.5. Vector Widening Floating-Point Multiply 393912e2179SXuan Hu VFWMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 394b448988dSczw 395b448988dSczw // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 396912e2179SXuan Hu VFMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 397912e2179SXuan Hu VFNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 398912e2179SXuan Hu VFMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 399912e2179SXuan Hu VFNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 400912e2179SXuan Hu VFMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 401912e2179SXuan Hu VFNMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 402912e2179SXuan Hu VFMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 403912e2179SXuan Hu VFNMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 404b448988dSczw 405b448988dSczw // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 406912e2179SXuan Hu VFWMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 407912e2179SXuan Hu VFWNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 408912e2179SXuan Hu VFWMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 409912e2179SXuan Hu VFWNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 410b448988dSczw 411b448988dSczw // 13.8. Vector Floating-Point Square-Root Instruction 412912e2179SXuan Hu VFSQRT_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 413b448988dSczw 414b448988dSczw // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 415912e2179SXuan Hu VFRSQRT7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 416b448988dSczw 417b448988dSczw // 13.10. Vector Floating-Point Reciprocal Estimate Instruction 418912e2179SXuan Hu VFREC7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 419b448988dSczw 420b448988dSczw // 13.11. Vector Floating-Point MIN/MAX Instructions 421912e2179SXuan Hu VFMIN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 422912e2179SXuan Hu VFMAX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 423b448988dSczw 424b448988dSczw // 13.12. Vector Floating-Point Sign-Injection Instructions 425912e2179SXuan Hu VFSGNJ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 426912e2179SXuan Hu VFSGNJN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 427912e2179SXuan Hu VFSGNJX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 428b448988dSczw 429b448988dSczw // 13.13. Vector Floating-Point Compare Instructions 430912e2179SXuan Hu VMFEQ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 431912e2179SXuan Hu VMFNE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 432912e2179SXuan Hu VMFLT_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 433912e2179SXuan Hu VMFLE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 434b448988dSczw 435b448988dSczw // 13.14. Vector Floating-Point Classify Instruction 436912e2179SXuan Hu VFCLASS_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 437b448988dSczw 438b448988dSczw // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 439912e2179SXuan Hu VFCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 440912e2179SXuan Hu VFCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 441912e2179SXuan Hu VFCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 442912e2179SXuan Hu VFCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 443912e2179SXuan Hu VFCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 444912e2179SXuan Hu VFCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 445b448988dSczw 446b448988dSczw // 13.18. Widening Floating-Point/Integer Type-Convert Instructions 447912e2179SXuan Hu VFWCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 448912e2179SXuan Hu VFWCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 449912e2179SXuan Hu VFWCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 450912e2179SXuan Hu VFWCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 451912e2179SXuan Hu VFWCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 452912e2179SXuan Hu VFWCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 453912e2179SXuan Hu VFWCVT_F_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 454b448988dSczw 455*b65b9ebaSXuan Hu // ! 456b448988dSczw // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 457912e2179SXuan Hu VFNCVT_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 458912e2179SXuan Hu VFNCVT_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 459912e2179SXuan Hu VFNCVT_RTZ_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 460912e2179SXuan Hu VFNCVT_RTZ_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 461912e2179SXuan Hu VFNCVT_F_XU_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 462912e2179SXuan Hu VFNCVT_F_X_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 463912e2179SXuan Hu VFNCVT_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 464912e2179SXuan Hu VFNCVT_ROD_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 465b448988dSczw 466b448988dSczw // 14.3. Vector Single-Width Floating-Point Reduction Instructions 467912e2179SXuan Hu VFREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 468912e2179SXuan Hu VFREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 469912e2179SXuan Hu VFREDMAX_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 470912e2179SXuan Hu VFREDMIN_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 471b448988dSczw 472b448988dSczw // 14.4. Vector Widening Floating-Point Reduction Instructions 473912e2179SXuan Hu VFWREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 474912e2179SXuan Hu VFWREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 475b448988dSczw 476b448988dSczw // 16.2. Floating-Point Scalar Move Instructions 477912e2179SXuan Hu VFMV_F_S -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// f[rd] = vs2[0] (rs1=0) 478b448988dSczw ) 4797f2b7720SXuan Hu 480*b65b9ebaSXuan Hu val opfvf: Array[(BitPat, XSDecodeBase)] = Array( 481b448988dSczw // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 482912e2179SXuan Hu VFADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 483912e2179SXuan Hu VFSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 484912e2179SXuan Hu VFRSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 485b448988dSczw 486b448988dSczw // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 487912e2179SXuan Hu VFWADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 488912e2179SXuan Hu VFWSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 489912e2179SXuan Hu VFWADD_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 490912e2179SXuan Hu VFWSUB_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 491b448988dSczw 492b448988dSczw // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 493912e2179SXuan Hu VFMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 494912e2179SXuan Hu VFDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 495912e2179SXuan Hu VFRDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 496b448988dSczw 497b448988dSczw // 13.5. Vector Widening Floating-Point Multiply 498912e2179SXuan Hu VFWMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 499b448988dSczw 500b448988dSczw // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 501912e2179SXuan Hu VFMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 502912e2179SXuan Hu VFNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 503912e2179SXuan Hu VFMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 504912e2179SXuan Hu VFNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 505912e2179SXuan Hu VFMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 506912e2179SXuan Hu VFNMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 507912e2179SXuan Hu VFMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 508912e2179SXuan Hu VFNMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 509b448988dSczw 510b448988dSczw // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 511912e2179SXuan Hu VFWMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 512912e2179SXuan Hu VFWNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 513912e2179SXuan Hu VFWMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 514912e2179SXuan Hu VFWNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 515b448988dSczw 516b448988dSczw // 13.11. Vector Floating-Point MIN/MAX Instructions 517912e2179SXuan Hu VFMIN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 518912e2179SXuan Hu VFMAX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 519b448988dSczw 520b448988dSczw // 13.12. Vector Floating-Point Sign-Injection Instructions 521912e2179SXuan Hu VFSGNJ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 522912e2179SXuan Hu VFSGNJN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 523912e2179SXuan Hu VFSGNJX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 524b448988dSczw 525b448988dSczw // 13.13. Vector Floating-Point Compare Instructions 526912e2179SXuan Hu VMFEQ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 527912e2179SXuan Hu VMFNE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 528912e2179SXuan Hu VMFLT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 529912e2179SXuan Hu VMFLE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 530912e2179SXuan Hu VMFGT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 531912e2179SXuan Hu VMFGE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 532b448988dSczw 533b448988dSczw // 13.15. Vector Floating-Point Merge Instruction 534912e2179SXuan Hu VFMERGE_VFM -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 535b448988dSczw 536b448988dSczw // 13.16. Vector Floating-Point Move Instruction 537912e2179SXuan Hu VFMV_V_F -> OPFVF(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// src2=SrcType.X 538b448988dSczw 539b448988dSczw // 16.2. Floating-Point Scalar Move Instructions 540912e2179SXuan Hu VFMV_S_F -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vs2=0 541b448988dSczw 542b448988dSczw // 16.3.3. Vector Slide1up 543b448988dSczw // vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] 544912e2179SXuan Hu VFSLIDE1UP_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[0]=f[rs1], vd[i+1] = vs2[i] 545b448988dSczw 546b448988dSczw // 16.3.4. Vector Slide1down Instruction 547b448988dSczw // vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] 548912e2179SXuan Hu VFSLIDE1DOWN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1] 5497f2b7720SXuan Hu ) 5507f2b7720SXuan Hu 551*b65b9ebaSXuan Hu val vset: Array[(BitPat, XSDecodeBase)] = Array( 552912e2179SXuan Hu VSETVLI -> VSET(F, T, ALUOpType.vsetvli, F, SelImm.IMM_VSETVLI), 553912e2179SXuan Hu VSETIVLI -> VSET(T, T, ALUOpType.vsetivli, F, SelImm.IMM_VSETIVLI), 554912e2179SXuan Hu VSETVL -> VSET(F, F, ALUOpType.vsetvl, T, SelImm.X), // flush pipe 555912e2179SXuan Hu ) 5567f2b7720SXuan Hu 557*b65b9ebaSXuan Hu val vls: Array[(BitPat, XSDecodeBase)] = Array( 558912e2179SXuan Hu // 7.4. Vector Unit-Stride Instructions 559912e2179SXuan Hu VLE8_V -> VLD(SrcType.X, VlduType.dummy), 560912e2179SXuan Hu VLE16_V -> VLD(SrcType.X, VlduType.dummy), 561912e2179SXuan Hu VLE32_V -> VLD(SrcType.X, VlduType.dummy), 562912e2179SXuan Hu VLE64_V -> VLD(SrcType.X, VlduType.dummy), 563912e2179SXuan Hu VSE8_V -> VST(SrcType.X, VstuType.dummy), 564912e2179SXuan Hu VSE16_V -> VST(SrcType.X, VstuType.dummy), 565912e2179SXuan Hu VSE32_V -> VST(SrcType.X, VstuType.dummy), 566912e2179SXuan Hu VSE64_V -> VST(SrcType.X, VstuType.dummy), 567912e2179SXuan Hu VLM_V -> VLD(SrcType.X, VlduType.dummy, mask = T), 568912e2179SXuan Hu VSM_V -> VST(SrcType.X, VstuType.dummy, mask = T), 569912e2179SXuan Hu // 7.5. Vector Strided Instructions 570912e2179SXuan Hu VLSE8_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 571912e2179SXuan Hu VLSE16_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 572912e2179SXuan Hu VLSE32_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 573912e2179SXuan Hu VLSE64_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 574912e2179SXuan Hu VSSE8_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 575912e2179SXuan Hu VSSE16_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 576912e2179SXuan Hu VSSE32_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 577912e2179SXuan Hu VSSE64_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 578912e2179SXuan Hu // 7.6. Vector Indexed Instructions 579912e2179SXuan Hu VLUXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 580912e2179SXuan Hu VLUXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 581912e2179SXuan Hu VLUXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 582912e2179SXuan Hu VLUXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 583912e2179SXuan Hu VLOXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 584912e2179SXuan Hu VLOXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 585912e2179SXuan Hu VLOXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 586912e2179SXuan Hu VLOXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 587912e2179SXuan Hu VSUXEI8_V -> VLD(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 588912e2179SXuan Hu VSUXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 589912e2179SXuan Hu VSUXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 590912e2179SXuan Hu VSUXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 591912e2179SXuan Hu VSOXEI8_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 592912e2179SXuan Hu VSOXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 593912e2179SXuan Hu VSOXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 594912e2179SXuan Hu VSOXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 595912e2179SXuan Hu // 7.7. Unit-stride Fault-Only-First Loads 596912e2179SXuan Hu VLE8FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 597912e2179SXuan Hu VLE16FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 598912e2179SXuan Hu VLE32FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 599912e2179SXuan Hu VLE64FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 600912e2179SXuan Hu // 7.8. Vector Load/Store Segment Instructions 601912e2179SXuan Hu // 7.8.1. Vector Unit-Stride Segment Loads and Stores 602912e2179SXuan Hu // TODO 603912e2179SXuan Hu // 7.8.2. Vector Strided Segment Loads and Stores 604912e2179SXuan Hu // TODO 605912e2179SXuan Hu // 7.8.3. Vector Indexed Segment Loads and Stores 606912e2179SXuan Hu // TODO 607912e2179SXuan Hu // 7.9. Vector Load/Store Whole Register Instructions 608912e2179SXuan Hu VL1RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 609912e2179SXuan Hu VL1RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 610912e2179SXuan Hu VL1RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 611912e2179SXuan Hu VL1RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 612912e2179SXuan Hu VL2RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 613912e2179SXuan Hu VL2RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 614912e2179SXuan Hu VL2RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 615912e2179SXuan Hu VL2RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 616912e2179SXuan Hu VL4RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 617912e2179SXuan Hu VL4RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 618912e2179SXuan Hu VL4RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 619912e2179SXuan Hu VL4RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 620912e2179SXuan Hu VL8RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 621912e2179SXuan Hu VL8RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 622912e2179SXuan Hu VL8RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 623912e2179SXuan Hu VL8RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 624912e2179SXuan Hu VS1R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 625912e2179SXuan Hu VS2R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 626912e2179SXuan Hu VS4R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 627912e2179SXuan Hu VS8R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 628912e2179SXuan Hu ) 629912e2179SXuan Hu 630*b65b9ebaSXuan Hu override val decodeArray: Array[(BitPat, XSDecodeBase)] = vset ++ vls ++ 631*b65b9ebaSXuan Hu opivv ++ opivx ++ opivi ++ opmvv ++ opmvx ++ opfvv ++ opfvf 6327f2b7720SXuan Hu} 633