17f2b7720SXuan Hupackage xiangshan.backend.decode 27f2b7720SXuan Hu 37f2b7720SXuan Huimport chipsalliance.rocketchip.config.Parameters 47f2b7720SXuan Huimport chisel3._ 5*912e2179SXuan Huimport chisel3.util.BitPat.bitPatToUInt 67f2b7720SXuan Huimport chisel3.util._ 77f2b7720SXuan Huimport freechips.rocketchip.util.uintToBitPat 83a2e64c4SZhangZifeiimport freechips.rocketchip.rocket.Instructions._ 97f2b7720SXuan Huimport utils._ 107f2b7720SXuan Huimport xiangshan.ExceptionNO.illegalInstr 117f2b7720SXuan Huimport xiangshan._ 12*912e2179SXuan Huimport yunsuan.{VfpuType, VipuType} 137f2b7720SXuan Hu 147f2b7720SXuan Huabstract class VecType { 157f2b7720SXuan Hu def X = BitPat("b?") 167f2b7720SXuan Hu def N = BitPat("b0") 177f2b7720SXuan Hu def Y = BitPat("b1") 187f2b7720SXuan Hu def generate() : List[BitPat] 197f2b7720SXuan Hu def asOldDecodeOutput(): List[BitPat] = { 20*912e2179SXuan Hu val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 217f2b7720SXuan Hu List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm) 227f2b7720SXuan Hu } 23*912e2179SXuan Hu def asFirstStageDecodeOutput(): List[BitPat] = { 24*912e2179SXuan Hu val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::vxsatWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 25*912e2179SXuan Hu List (src1, src2, src3, fu, fuOp, xWen, fWen, bitPatToUInt(vWen) | bitPatToUInt(mWen), xsTrap, noSpec, blockBack, flushPipe, selImm) 26*912e2179SXuan Hu } 277f2b7720SXuan Hu} 287f2b7720SXuan Hu 29*912e2179SXuan Hucase class OPIVV(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 307f2b7720SXuan Hu def generate() : List[BitPat] = { 31*912e2179SXuan Hu // xsTrap 32*912e2179SXuan Hu // | noSpec 33*912e2179SXuan Hu // xWen | | blockBack 34*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 35*912e2179SXuan Hu List (SrcType.vp, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 367f2b7720SXuan Hu } 377f2b7720SXuan Hu} 387f2b7720SXuan Hu 39*912e2179SXuan Hucase class OPIVX(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 4058c35d23Shuxuan0307 def generate() : List[BitPat] = { 41*912e2179SXuan Hu // xsTrap 42*912e2179SXuan Hu // | noSpec 43*912e2179SXuan Hu // xWen | | blockBack 44*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 45*912e2179SXuan Hu List (SrcType.xp, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 4658c35d23Shuxuan0307 } 477f2b7720SXuan Hu} 487f2b7720SXuan Hu 49*912e2179SXuan Hucase class OPIVI(src3: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean, selImm: BitPat) extends VecType { 5058c35d23Shuxuan0307 def generate() : List[BitPat] = { 51*912e2179SXuan Hu // xsTrap 52*912e2179SXuan Hu // | noSpec 53*912e2179SXuan Hu // xWen | | blockBack 54*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, |, fWen, vWen, mWen, vxsatWen, | | | flushPipe, selImm 55*912e2179SXuan Hu List (SrcType.imm, SrcType.vp, src3, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, selImm) 5658c35d23Shuxuan0307 } 577f2b7720SXuan Hu} 587f2b7720SXuan Hu 59*912e2179SXuan Hucase class OPMVV(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 60c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 617f2b7720SXuan Hu def generate() : List[BitPat] = { 62*912e2179SXuan Hu val vxsatWen = false 63*912e2179SXuan Hu // xsTrap 64*912e2179SXuan Hu // | noSpec 65*912e2179SXuan Hu // xWen fWen | | blockBack 66*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 67*912e2179SXuan Hu List (SrcType.vp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 687f2b7720SXuan Hu } 697f2b7720SXuan Hu} 707f2b7720SXuan Hu 71*912e2179SXuan Hucase class OPMVX(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 72c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 73c6661c33SHaojin Tang def generate() : List[BitPat] = { 74*912e2179SXuan Hu val vxsatWen = false 75*912e2179SXuan Hu // xsTrap 76*912e2179SXuan Hu // | noSpec 77*912e2179SXuan Hu // xWen fWen | | blockBack 78*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 79*912e2179SXuan Hu List (SrcType.xp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 80c6661c33SHaojin Tang } 817f2b7720SXuan Hu} 827f2b7720SXuan Hu 83b448988dSczwcase class OPFVV(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 84b448988dSczw def generate() : List[BitPat] = { 85*912e2179SXuan Hu val vxsatWen = false 86*912e2179SXuan Hu // xsTrap 87*912e2179SXuan Hu // | noSpec 88*912e2179SXuan Hu // xWen fWen | | blockBack 89*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 90*912e2179SXuan Hu List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 91b448988dSczw } 927f2b7720SXuan Hu} 937f2b7720SXuan Hu 94b448988dSczwcase class OPFVF(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 957f2b7720SXuan Hu def generate() : List[BitPat] = { 96*912e2179SXuan Hu val vxsatWen = false 97*912e2179SXuan Hu // xsTrap 98*912e2179SXuan Hu // | noSpec 99*912e2179SXuan Hu // xWen fWen | | blockBack 100*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | vWen mWen vxsatWen, | | | flushPipe, selImm 101*912e2179SXuan Hu List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, vxsatWen.B, N, N, N, N, SelImm.X) 1027f2b7720SXuan Hu } 1037f2b7720SXuan Hu} 1047f2b7720SXuan Hu 105*912e2179SXuan Hucase class VSET(vli: Boolean, vtypei: Boolean, fuOp: BitPat, flushPipe: Boolean, selImm: BitPat) extends VecType { 106*912e2179SXuan Hu def generate() : List[BitPat] = { 107*912e2179SXuan Hu val src1 = if (vli) SrcType.imm else SrcType.xp 108*912e2179SXuan Hu val src2 = if (vtypei) SrcType.imm else SrcType.xp 109*912e2179SXuan Hu // xWen 110*912e2179SXuan Hu // | fWen xsTrap 111*912e2179SXuan Hu // | | vWen | noSpec 112*912e2179SXuan Hu // | | | mWen | | blockBack 113*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 114*912e2179SXuan Hu List (src1, src2, SrcType.X, FuType.alu, fuOp, Y, N, N, N, N, N, N, N, Y, selImm) 115*912e2179SXuan Hu } 1167f2b7720SXuan Hu} 1177f2b7720SXuan Hu 118*912e2179SXuan Hucase class VLD(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, ff: Boolean = false, 119*912e2179SXuan Hu mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends VecType { 120*912e2179SXuan Hu def generate() : List[BitPat] = { 121*912e2179SXuan Hu val fu = FuType.vldu 122*912e2179SXuan Hu val src1 = SrcType.xp 123*912e2179SXuan Hu val src3 = SrcType.X 124*912e2179SXuan Hu // xWen 125*912e2179SXuan Hu // | fWen xsTrap 126*912e2179SXuan Hu // | | vWen | noSpec 127*912e2179SXuan Hu // | | | mWen | | blockBack 128*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 129*912e2179SXuan Hu List (src1, src2, src3, fu, fuOp, N, N, Y, N, N, N, N, N, Y, SelImm.X) 130*912e2179SXuan Hu } 131*912e2179SXuan Hu} 132*912e2179SXuan Hu 133*912e2179SXuan Hucase class VST(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Boolean = false, 134*912e2179SXuan Hu mask: Boolean = false, whole: Boolean = false, ordered: Boolean = false) extends VecType { 135*912e2179SXuan Hu def generate() : List[BitPat] = { 136*912e2179SXuan Hu val fu = FuType.vstu 137*912e2179SXuan Hu val src1 = SrcType.xp 138*912e2179SXuan Hu val src3 = SrcType.vp 139*912e2179SXuan Hu // xWen 140*912e2179SXuan Hu // | fWen xsTrap 141*912e2179SXuan Hu // | | vWen | noSpec 142*912e2179SXuan Hu // | | | mWen | | blockBack 143*912e2179SXuan Hu // src1, src2, src3, fu, fuOp, | | | | vxsatWen, | | | flushPipe, selImm 144*912e2179SXuan Hu List (src1, src2, src3, fu, fuOp, N, N, Y, N, N, N, N, N, Y, SelImm.X) 145*912e2179SXuan Hu } 1467f2b7720SXuan Hu} 1477f2b7720SXuan Hu 1487f2b7720SXuan Huobject VecDecoder extends DecodeConstants { 1497f2b7720SXuan Hu private def F = false 1507f2b7720SXuan Hu private def T = true 1517f2b7720SXuan Hu 152*912e2179SXuan Hu val opivv: Array[(BitPat, VecType)] = Array( 153*912e2179SXuan Hu VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 154*912e2179SXuan Hu VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 1557f2b7720SXuan Hu 156*912e2179SXuan Hu VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 157*912e2179SXuan Hu VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 158*912e2179SXuan Hu VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 159*912e2179SXuan Hu VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 16058c35d23Shuxuan0307 161*912e2179SXuan Hu VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 162*912e2179SXuan Hu VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 163*912e2179SXuan Hu VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 16458c35d23Shuxuan0307 165*912e2179SXuan Hu VRGATHER_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 166*912e2179SXuan Hu VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 16758c35d23Shuxuan0307 168*912e2179SXuan Hu VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 169*912e2179SXuan Hu VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 170*912e2179SXuan Hu VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 17158c35d23Shuxuan0307 172*912e2179SXuan Hu VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 173*912e2179SXuan Hu VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 174*912e2179SXuan Hu VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 17558c35d23Shuxuan0307 176*912e2179SXuan Hu VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 17758c35d23Shuxuan0307 178*912e2179SXuan Hu VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 179*912e2179SXuan Hu VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 180*912e2179SXuan Hu VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 181*912e2179SXuan Hu VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 182*912e2179SXuan Hu VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 183*912e2179SXuan Hu VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 18458c35d23Shuxuan0307 185*912e2179SXuan Hu VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 186*912e2179SXuan Hu VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 187*912e2179SXuan Hu VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 188*912e2179SXuan Hu VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 189*912e2179SXuan Hu VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 19058c35d23Shuxuan0307 191*912e2179SXuan Hu VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 192*912e2179SXuan Hu VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 193*912e2179SXuan Hu VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 194*912e2179SXuan Hu VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 19558c35d23Shuxuan0307 196*912e2179SXuan Hu VSMUL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 19758c35d23Shuxuan0307 198*912e2179SXuan Hu VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 199*912e2179SXuan Hu VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 20058c35d23Shuxuan0307 201*912e2179SXuan Hu VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 202*912e2179SXuan Hu VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 20358c35d23Shuxuan0307 204*912e2179SXuan Hu VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 205*912e2179SXuan Hu VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 2067f2b7720SXuan Hu ) 2077f2b7720SXuan Hu 208*912e2179SXuan Hu val opivx: Array[(BitPat, VecType)] = Array( 209*912e2179SXuan Hu VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 210*912e2179SXuan Hu VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 211*912e2179SXuan Hu VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 21258c35d23Shuxuan0307 213*912e2179SXuan Hu VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 214*912e2179SXuan Hu VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 215*912e2179SXuan Hu VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 216*912e2179SXuan Hu VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 21758c35d23Shuxuan0307 218*912e2179SXuan Hu VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 219*912e2179SXuan Hu VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 220*912e2179SXuan Hu VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 22158c35d23Shuxuan0307 222*912e2179SXuan Hu VRGATHER_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 22358c35d23Shuxuan0307 224*912e2179SXuan Hu VSLIDEUP_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 225*912e2179SXuan Hu VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 22658c35d23Shuxuan0307 227*912e2179SXuan Hu VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 228*912e2179SXuan Hu VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 229*912e2179SXuan Hu VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 230*912e2179SXuan Hu VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 231*912e2179SXuan Hu VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), 23258c35d23Shuxuan0307 233*912e2179SXuan Hu VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), 23458c35d23Shuxuan0307 235*912e2179SXuan Hu VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 236*912e2179SXuan Hu VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 237*912e2179SXuan Hu VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 238*912e2179SXuan Hu VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 239*912e2179SXuan Hu VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 240*912e2179SXuan Hu VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 241*912e2179SXuan Hu VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 242*912e2179SXuan Hu VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), 24358c35d23Shuxuan0307 244*912e2179SXuan Hu VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 245*912e2179SXuan Hu VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 246*912e2179SXuan Hu VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 247*912e2179SXuan Hu VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 248*912e2179SXuan Hu VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 24958c35d23Shuxuan0307 250*912e2179SXuan Hu VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 251*912e2179SXuan Hu VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 252*912e2179SXuan Hu VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 253*912e2179SXuan Hu VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 25458c35d23Shuxuan0307 25558c35d23Shuxuan0307 256*912e2179SXuan Hu VSMUL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 25758c35d23Shuxuan0307 258*912e2179SXuan Hu VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 259*912e2179SXuan Hu VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), 26058c35d23Shuxuan0307 261*912e2179SXuan Hu VNCLIPU_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 262*912e2179SXuan Hu VNCLIP_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), 26358c35d23Shuxuan0307 ) 26458c35d23Shuxuan0307 265*912e2179SXuan Hu val opivi: Array[(BitPat, VecType)] = Array( 266*912e2179SXuan Hu VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 267*912e2179SXuan Hu VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 26858c35d23Shuxuan0307 269*912e2179SXuan Hu VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 270*912e2179SXuan Hu VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 271*912e2179SXuan Hu VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 27258c35d23Shuxuan0307 273*912e2179SXuan Hu VRGATHER_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 27458c35d23Shuxuan0307 275*912e2179SXuan Hu VSLIDEUP_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 276*912e2179SXuan Hu VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 27758c35d23Shuxuan0307 278*912e2179SXuan Hu VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 279*912e2179SXuan Hu VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 28058c35d23Shuxuan0307 281*912e2179SXuan Hu VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 28258c35d23Shuxuan0307 283*912e2179SXuan Hu VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 284*912e2179SXuan Hu VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 285*912e2179SXuan Hu VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 286*912e2179SXuan Hu VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 287*912e2179SXuan Hu VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 288*912e2179SXuan Hu VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), 28958c35d23Shuxuan0307 290*912e2179SXuan Hu VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 291*912e2179SXuan Hu VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 292*912e2179SXuan Hu VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 293*912e2179SXuan Hu VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 294*912e2179SXuan Hu VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 29558c35d23Shuxuan0307 296*912e2179SXuan Hu VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 297*912e2179SXuan Hu VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), 29858c35d23Shuxuan0307 299*912e2179SXuan Hu VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 300*912e2179SXuan Hu VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), 30158c35d23Shuxuan0307 302*912e2179SXuan Hu VNCLIPU_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 303*912e2179SXuan Hu VNCLIP_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), 30458c35d23Shuxuan0307 305*912e2179SXuan Hu VMV1R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 306*912e2179SXuan Hu VMV2R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 307*912e2179SXuan Hu VMV4R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 308*912e2179SXuan Hu VMV8R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), 30958c35d23Shuxuan0307 ) 3107f2b7720SXuan Hu 311*912e2179SXuan Hu val opmvv: Array[(BitPat, VecType)] = Array( 312*912e2179SXuan Hu VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 313*912e2179SXuan Hu VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 314*912e2179SXuan Hu VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 315*912e2179SXuan Hu VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 316*912e2179SXuan Hu VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 317*912e2179SXuan Hu VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 318*912e2179SXuan Hu VDIV_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 319*912e2179SXuan Hu VDIVU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 320*912e2179SXuan Hu VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 321*912e2179SXuan Hu VID_V -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 322*912e2179SXuan Hu VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 323*912e2179SXuan Hu VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 324*912e2179SXuan Hu VMADD_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 325*912e2179SXuan Hu VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 326*912e2179SXuan Hu VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 327*912e2179SXuan Hu VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 328*912e2179SXuan Hu VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 329*912e2179SXuan Hu VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 330*912e2179SXuan Hu VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 331*912e2179SXuan Hu VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 332*912e2179SXuan Hu VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 333*912e2179SXuan Hu VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 334*912e2179SXuan Hu VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 335*912e2179SXuan Hu VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 336*912e2179SXuan Hu VMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 337*912e2179SXuan Hu VMULH_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 338*912e2179SXuan Hu VMULHSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 339*912e2179SXuan Hu VMULHU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 340*912e2179SXuan Hu VMV_X_S -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), 341*912e2179SXuan Hu VNMSAC_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 342*912e2179SXuan Hu VNMSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 343*912e2179SXuan Hu VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 344*912e2179SXuan Hu VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 345*912e2179SXuan Hu VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 346*912e2179SXuan Hu VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 347*912e2179SXuan Hu VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 348*912e2179SXuan Hu VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 349*912e2179SXuan Hu VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 350*912e2179SXuan Hu VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 351*912e2179SXuan Hu VREM_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 352*912e2179SXuan Hu VREMU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 353*912e2179SXuan Hu VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 354*912e2179SXuan Hu VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 355*912e2179SXuan Hu VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 356*912e2179SXuan Hu VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 357*912e2179SXuan Hu VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 358*912e2179SXuan Hu VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 359*912e2179SXuan Hu VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 360*912e2179SXuan Hu VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 361*912e2179SXuan Hu VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 362*912e2179SXuan Hu VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 363*912e2179SXuan Hu VWMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 364*912e2179SXuan Hu VWMACCSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 365*912e2179SXuan Hu VWMACCU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), 366*912e2179SXuan Hu VWMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 367*912e2179SXuan Hu VWMULSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 368*912e2179SXuan Hu VWMULU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 369*912e2179SXuan Hu VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 370*912e2179SXuan Hu VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 371*912e2179SXuan Hu VWSUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), 372*912e2179SXuan Hu VWSUBU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F) 373c6661c33SHaojin Tang ) 374*912e2179SXuan Hu 375*912e2179SXuan Hu val opmvx: Array[(BitPat, VecType)] = Array( 376*912e2179SXuan Hu VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 377*912e2179SXuan Hu VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 378*912e2179SXuan Hu VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 379*912e2179SXuan Hu VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 380*912e2179SXuan Hu VDIV_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 381*912e2179SXuan Hu VDIVU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 382*912e2179SXuan Hu VMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 383*912e2179SXuan Hu VMADD_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 384*912e2179SXuan Hu VMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 385*912e2179SXuan Hu VMULH_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 386*912e2179SXuan Hu VMULHSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 387*912e2179SXuan Hu VMULHU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 388*912e2179SXuan Hu VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 389*912e2179SXuan Hu VNMSAC_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 390*912e2179SXuan Hu VNMSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 391*912e2179SXuan Hu VREM_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 392*912e2179SXuan Hu VREMU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 393*912e2179SXuan Hu VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 394*912e2179SXuan Hu VSLIDE1UP_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 395*912e2179SXuan Hu VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 396*912e2179SXuan Hu VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 397*912e2179SXuan Hu VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 398*912e2179SXuan Hu VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 399*912e2179SXuan Hu VWMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 400*912e2179SXuan Hu VWMACCSU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 401*912e2179SXuan Hu VWMACCU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 402*912e2179SXuan Hu VWMACCUS_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), 403*912e2179SXuan Hu VWMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 404*912e2179SXuan Hu VWMULSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 405*912e2179SXuan Hu VWMULU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 406*912e2179SXuan Hu VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 407*912e2179SXuan Hu VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 408*912e2179SXuan Hu VWSUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), 409*912e2179SXuan Hu VWSUBU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F) 410c6661c33SHaojin Tang ) 4117f2b7720SXuan Hu 412*912e2179SXuan Hu val opfvv: Array[(BitPat, VecType)] = Array( 413b448988dSczw // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 414*912e2179SXuan Hu VFADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 415*912e2179SXuan Hu VFSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 416b448988dSczw 417b448988dSczw // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 418*912e2179SXuan Hu VFWADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 419*912e2179SXuan Hu VFWSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 420*912e2179SXuan Hu VFWADD_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 421*912e2179SXuan Hu VFWSUB_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 422b448988dSczw 423b448988dSczw // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 424*912e2179SXuan Hu VFMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 425*912e2179SXuan Hu VFDIV_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 426b448988dSczw 427b448988dSczw // 13.5. Vector Widening Floating-Point Multiply 428*912e2179SXuan Hu VFWMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 429b448988dSczw 430b448988dSczw // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 431*912e2179SXuan Hu VFMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 432*912e2179SXuan Hu VFNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 433*912e2179SXuan Hu VFMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 434*912e2179SXuan Hu VFNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 435*912e2179SXuan Hu VFMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 436*912e2179SXuan Hu VFNMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 437*912e2179SXuan Hu VFMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 438*912e2179SXuan Hu VFNMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 439b448988dSczw 440b448988dSczw // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 441*912e2179SXuan Hu VFWMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 442*912e2179SXuan Hu VFWNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 443*912e2179SXuan Hu VFWMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 444*912e2179SXuan Hu VFWNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 445b448988dSczw 446b448988dSczw // 13.8. Vector Floating-Point Square-Root Instruction 447*912e2179SXuan Hu VFSQRT_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 448b448988dSczw 449b448988dSczw // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 450*912e2179SXuan Hu VFRSQRT7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 451b448988dSczw 452b448988dSczw // 13.10. Vector Floating-Point Reciprocal Estimate Instruction 453*912e2179SXuan Hu VFREC7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 454b448988dSczw 455b448988dSczw // 13.11. Vector Floating-Point MIN/MAX Instructions 456*912e2179SXuan Hu VFMIN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 457*912e2179SXuan Hu VFMAX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 458b448988dSczw 459b448988dSczw // 13.12. Vector Floating-Point Sign-Injection Instructions 460*912e2179SXuan Hu VFSGNJ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 461*912e2179SXuan Hu VFSGNJN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 462*912e2179SXuan Hu VFSGNJX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 463b448988dSczw 464b448988dSczw // 13.13. Vector Floating-Point Compare Instructions 465*912e2179SXuan Hu VMFEQ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 466*912e2179SXuan Hu VMFNE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 467*912e2179SXuan Hu VMFLT_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 468*912e2179SXuan Hu VMFLE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 469b448988dSczw 470b448988dSczw // 13.14. Vector Floating-Point Classify Instruction 471*912e2179SXuan Hu VFCLASS_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 472b448988dSczw 473b448988dSczw // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 474*912e2179SXuan Hu VFCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 475*912e2179SXuan Hu VFCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 476*912e2179SXuan Hu VFCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 477*912e2179SXuan Hu VFCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 478*912e2179SXuan Hu VFCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 479*912e2179SXuan Hu VFCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 480b448988dSczw 481b448988dSczw // 13.18. Widening Floating-Point/Integer Type-Convert Instructions 482*912e2179SXuan Hu VFWCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 483*912e2179SXuan Hu VFWCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 484*912e2179SXuan Hu VFWCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 485*912e2179SXuan Hu VFWCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 486*912e2179SXuan Hu VFWCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 487*912e2179SXuan Hu VFWCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 488*912e2179SXuan Hu VFWCVT_F_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 489b448988dSczw 490b448988dSczw // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 491*912e2179SXuan Hu VFNCVT_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 492*912e2179SXuan Hu VFNCVT_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 493*912e2179SXuan Hu VFNCVT_RTZ_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 494*912e2179SXuan Hu VFNCVT_RTZ_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 495*912e2179SXuan Hu VFNCVT_F_XU_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 496*912e2179SXuan Hu VFNCVT_F_X_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 497*912e2179SXuan Hu VFNCVT_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 498*912e2179SXuan Hu VFNCVT_ROD_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 499b448988dSczw 500b448988dSczw // 14.3. Vector Single-Width Floating-Point Reduction Instructions 501*912e2179SXuan Hu VFREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 502*912e2179SXuan Hu VFREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 503*912e2179SXuan Hu VFREDMAX_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 504*912e2179SXuan Hu VFREDMIN_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 505b448988dSczw 506b448988dSczw // 14.4. Vector Widening Floating-Point Reduction Instructions 507*912e2179SXuan Hu VFWREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 508*912e2179SXuan Hu VFWREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 509b448988dSczw 510b448988dSczw // 16.2. Floating-Point Scalar Move Instructions 511*912e2179SXuan Hu VFMV_F_S -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// f[rd] = vs2[0] (rs1=0) 512b448988dSczw ) 5137f2b7720SXuan Hu 514*912e2179SXuan Hu val opfvf: Array[(BitPat, VecType)] = Array( 515b448988dSczw // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 516*912e2179SXuan Hu VFADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 517*912e2179SXuan Hu VFSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 518*912e2179SXuan Hu VFRSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 519b448988dSczw 520b448988dSczw // 13.3. Vector Widening Floating-Point Add/Subtract Instructions 521*912e2179SXuan Hu VFWADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 522*912e2179SXuan Hu VFWSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 523*912e2179SXuan Hu VFWADD_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 524*912e2179SXuan Hu VFWSUB_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 525b448988dSczw 526b448988dSczw // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 527*912e2179SXuan Hu VFMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 528*912e2179SXuan Hu VFDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 529*912e2179SXuan Hu VFRDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 530b448988dSczw 531b448988dSczw // 13.5. Vector Widening Floating-Point Multiply 532*912e2179SXuan Hu VFWMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 533b448988dSczw 534b448988dSczw // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 535*912e2179SXuan Hu VFMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 536*912e2179SXuan Hu VFNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 537*912e2179SXuan Hu VFMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 538*912e2179SXuan Hu VFNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 539*912e2179SXuan Hu VFMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 540*912e2179SXuan Hu VFNMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 541*912e2179SXuan Hu VFMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 542*912e2179SXuan Hu VFNMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 543b448988dSczw 544b448988dSczw // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 545*912e2179SXuan Hu VFWMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 546*912e2179SXuan Hu VFWNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 547*912e2179SXuan Hu VFWMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 548*912e2179SXuan Hu VFWNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F), 549b448988dSczw 550b448988dSczw // 13.11. Vector Floating-Point MIN/MAX Instructions 551*912e2179SXuan Hu VFMIN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 552*912e2179SXuan Hu VFMAX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 553b448988dSczw 554b448988dSczw // 13.12. Vector Floating-Point Sign-Injection Instructions 555*912e2179SXuan Hu VFSGNJ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 556*912e2179SXuan Hu VFSGNJN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 557*912e2179SXuan Hu VFSGNJX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 558b448988dSczw 559b448988dSczw // 13.13. Vector Floating-Point Compare Instructions 560*912e2179SXuan Hu VMFEQ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 561*912e2179SXuan Hu VMFNE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 562*912e2179SXuan Hu VMFLT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 563*912e2179SXuan Hu VMFLE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 564*912e2179SXuan Hu VMFGT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 565*912e2179SXuan Hu VMFGE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T), 566b448988dSczw 567b448988dSczw // 13.15. Vector Floating-Point Merge Instruction 568*912e2179SXuan Hu VFMERGE_VFM -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F), 569b448988dSczw 570b448988dSczw // 13.16. Vector Floating-Point Move Instruction 571*912e2179SXuan Hu VFMV_V_F -> OPFVF(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// src2=SrcType.X 572b448988dSczw 573b448988dSczw // 16.2. Floating-Point Scalar Move Instructions 574*912e2179SXuan Hu VFMV_S_F -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vs2=0 575b448988dSczw 576b448988dSczw // 16.3.3. Vector Slide1up 577b448988dSczw // vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] 578*912e2179SXuan Hu VFSLIDE1UP_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[0]=f[rs1], vd[i+1] = vs2[i] 579b448988dSczw 580b448988dSczw // 16.3.4. Vector Slide1down Instruction 581b448988dSczw // vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] 582*912e2179SXuan Hu VFSLIDE1DOWN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1] 5837f2b7720SXuan Hu ) 5847f2b7720SXuan Hu 585*912e2179SXuan Hu val vset: Array[(BitPat, VecType)] = Array( 586*912e2179SXuan Hu VSETVLI -> VSET(F, T, ALUOpType.vsetvli, F, SelImm.IMM_VSETVLI), 587*912e2179SXuan Hu VSETIVLI -> VSET(T, T, ALUOpType.vsetivli, F, SelImm.IMM_VSETIVLI), 588*912e2179SXuan Hu VSETVL -> VSET(F, F, ALUOpType.vsetvl, T, SelImm.X), // flush pipe 589*912e2179SXuan Hu ) 5907f2b7720SXuan Hu 591*912e2179SXuan Hu val vls: Array[(BitPat, VecType)] = Array( 592*912e2179SXuan Hu // 7.4. Vector Unit-Stride Instructions 593*912e2179SXuan Hu VLE8_V -> VLD(SrcType.X, VlduType.dummy), 594*912e2179SXuan Hu VLE16_V -> VLD(SrcType.X, VlduType.dummy), 595*912e2179SXuan Hu VLE32_V -> VLD(SrcType.X, VlduType.dummy), 596*912e2179SXuan Hu VLE64_V -> VLD(SrcType.X, VlduType.dummy), 597*912e2179SXuan Hu VSE8_V -> VST(SrcType.X, VstuType.dummy), 598*912e2179SXuan Hu VSE16_V -> VST(SrcType.X, VstuType.dummy), 599*912e2179SXuan Hu VSE32_V -> VST(SrcType.X, VstuType.dummy), 600*912e2179SXuan Hu VSE64_V -> VST(SrcType.X, VstuType.dummy), 601*912e2179SXuan Hu VLM_V -> VLD(SrcType.X, VlduType.dummy, mask = T), 602*912e2179SXuan Hu VSM_V -> VST(SrcType.X, VstuType.dummy, mask = T), 603*912e2179SXuan Hu // 7.5. Vector Strided Instructions 604*912e2179SXuan Hu VLSE8_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 605*912e2179SXuan Hu VLSE16_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 606*912e2179SXuan Hu VLSE32_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 607*912e2179SXuan Hu VLSE64_V -> VLD(SrcType.xp, VlduType.dummy, strided = T), 608*912e2179SXuan Hu VSSE8_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 609*912e2179SXuan Hu VSSE16_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 610*912e2179SXuan Hu VSSE32_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 611*912e2179SXuan Hu VSSE64_V -> VST(SrcType.xp, VstuType.dummy, strided = T), 612*912e2179SXuan Hu // 7.6. Vector Indexed Instructions 613*912e2179SXuan Hu VLUXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 614*912e2179SXuan Hu VLUXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 615*912e2179SXuan Hu VLUXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 616*912e2179SXuan Hu VLUXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = F), 617*912e2179SXuan Hu VLOXEI8_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 618*912e2179SXuan Hu VLOXEI16_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 619*912e2179SXuan Hu VLOXEI32_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 620*912e2179SXuan Hu VLOXEI64_V -> VLD(SrcType.vp, VlduType.dummy, indexed = T, ordered = T), 621*912e2179SXuan Hu VSUXEI8_V -> VLD(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 622*912e2179SXuan Hu VSUXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 623*912e2179SXuan Hu VSUXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 624*912e2179SXuan Hu VSUXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = F), 625*912e2179SXuan Hu VSOXEI8_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 626*912e2179SXuan Hu VSOXEI16_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 627*912e2179SXuan Hu VSOXEI32_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 628*912e2179SXuan Hu VSOXEI64_V -> VST(SrcType.vp, VstuType.dummy, indexed = T, ordered = T), 629*912e2179SXuan Hu // 7.7. Unit-stride Fault-Only-First Loads 630*912e2179SXuan Hu VLE8FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 631*912e2179SXuan Hu VLE16FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 632*912e2179SXuan Hu VLE32FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 633*912e2179SXuan Hu VLE64FF_V -> VLD(SrcType.X, VlduType.dummy, ff = T), 634*912e2179SXuan Hu // 7.8. Vector Load/Store Segment Instructions 635*912e2179SXuan Hu // 7.8.1. Vector Unit-Stride Segment Loads and Stores 636*912e2179SXuan Hu // TODO 637*912e2179SXuan Hu // 7.8.2. Vector Strided Segment Loads and Stores 638*912e2179SXuan Hu // TODO 639*912e2179SXuan Hu // 7.8.3. Vector Indexed Segment Loads and Stores 640*912e2179SXuan Hu // TODO 641*912e2179SXuan Hu // 7.9. Vector Load/Store Whole Register Instructions 642*912e2179SXuan Hu VL1RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 643*912e2179SXuan Hu VL1RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 644*912e2179SXuan Hu VL1RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 645*912e2179SXuan Hu VL1RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 646*912e2179SXuan Hu VL2RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 647*912e2179SXuan Hu VL2RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 648*912e2179SXuan Hu VL2RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 649*912e2179SXuan Hu VL2RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 650*912e2179SXuan Hu VL4RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 651*912e2179SXuan Hu VL4RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 652*912e2179SXuan Hu VL4RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 653*912e2179SXuan Hu VL4RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 654*912e2179SXuan Hu VL8RE8_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 655*912e2179SXuan Hu VL8RE16_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 656*912e2179SXuan Hu VL8RE32_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 657*912e2179SXuan Hu VL8RE64_V -> VLD(SrcType.X, VlduType.dummy, whole = T), 658*912e2179SXuan Hu VS1R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 659*912e2179SXuan Hu VS2R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 660*912e2179SXuan Hu VS4R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 661*912e2179SXuan Hu VS8R_V -> VST(SrcType.X, VlduType.dummy, whole = T), 662*912e2179SXuan Hu ) 663*912e2179SXuan Hu 664*912e2179SXuan Hu val opivvTable : Array[(BitPat, List[BitPat])] = opivv.map(x => (x._1, x._2.generate())) 665*912e2179SXuan Hu val opivxTable : Array[(BitPat, List[BitPat])] = opivx.map(x => (x._1, x._2.generate())) 666*912e2179SXuan Hu val opiviTable : Array[(BitPat, List[BitPat])] = opivi.map(x => (x._1, x._2.generate())) 667*912e2179SXuan Hu val opmvvTable : Array[(BitPat, List[BitPat])] = opmvv.map(x => (x._1, x._2.generate())) 668*912e2179SXuan Hu val opmvxTable : Array[(BitPat, List[BitPat])] = opmvx.map(x => (x._1, x._2.generate())) 669*912e2179SXuan Hu val opfvvTable : Array[(BitPat, List[BitPat])] = opfvv.map(x => (x._1, x._2.generate())) 670*912e2179SXuan Hu val opfvfTable : Array[(BitPat, List[BitPat])] = opfvv.map(x => (x._1, x._2.generate())) 671*912e2179SXuan Hu val vsetTable : Array[(BitPat, List[BitPat])] = vset.map(x => (x._1, x._2.generate())) 672*912e2179SXuan Hu val vlsTable : Array[(BitPat, List[BitPat])] = vls.map(x => (x._1, x._2.generate())) 673*912e2179SXuan Hu 674*912e2179SXuan Hu val table: Array[(BitPat, List[BitPat])] = opivvTable ++ opivxTable ++ opiviTable ++ 6757f2b7720SXuan Hu opmvvTable ++ opmvxTable ++ 6767f2b7720SXuan Hu opfvvTable ++ opfvfTable ++ 6777f2b7720SXuan Hu vsetTable ++ vlsTable 6787f2b7720SXuan Hu} 679